rcc::Instance

CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+ - Add `rcc::Instance` trait
+
 ## [v0.23.0] - 2025-09-22
 
  - Implement `embedded_hal::i2c::I2c` for `I2cMasterDma` [#838]

src/adc.rs

@@ -138,7 +138,6 @@ use crate::{
     signature::VDDA_CALIB,
 };
 use core::fmt;
-use core::ops::Deref;
 
 pub mod config;
 mod f4;
@@ -153,10 +152,7 @@ pub struct Vbat;
 pub struct Temperature;
 
 /// Marker trait for all ADC peripherals
-pub trait Instance:
-    crate::Sealed + Deref<Target = pac::adc1::RegisterBlock> + rcc::Enable + rcc::Reset
-{
-}
+pub trait Instance: rcc::Instance + crate::Ptr<RB = pac::adc1::RegisterBlock> {}
 
 #[doc(hidden)]
 pub trait Calibrate {

src/can.rs

@@ -5,7 +5,7 @@ use crate::gpio;
 use crate::pac::{self, RCC};
 use crate::rcc;
 
-pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + gpio::alt::CanCommon {}
+pub trait Instance: rcc::Instance + gpio::alt::CanCommon {}
 
 macro_rules! can {
     ($CAN:ty: $Can:ident) => {

src/dma/traits.rs

@@ -3,7 +3,6 @@ use crate::{
     pac::{self, DMA1, DMA2},
     timer,
 };
-use core::ops::Deref;
 use enumflags2::BitFlags;
 
 pub(crate) mod sealed {
@@ -302,10 +301,7 @@ use address;
 pub type DMARegisterBlock = pac::dma1::RegisterBlock;
 
 /// Trait that represents an instance of a DMA peripheral.
-pub trait Instance:
-    crate::Sealed + crate::Ptr<RB = DMARegisterBlock> + Deref<Target = Self::RB>
-{
-}
+pub trait Instance: rcc::Instance + crate::Ptr<RB = DMARegisterBlock> {}
 
 impl Instance for DMA1 {}
 impl Instance for DMA2 {}

src/fmc.rs

@@ -7,7 +7,7 @@
 use stm32_fmc::FmcPeripheral;
 use stm32_fmc::{AddressPinSet, PinsSdram, Sdram, SdramChip, SdramPinSet, SdramTargetBank};
 
-use crate::rcc::{BusClock, Clocks, Enable, Reset};
+use crate::rcc::{BusClock, Clocks, Enable, RccBus, Reset};
 use fugit::HertzU32 as Hertz;
 
 use crate::gpio::alt::fmc as alt;
@@ -60,7 +60,7 @@ impl FmcExt for FMC_PER {
     fn fmc(self, clocks: &Clocks) -> FMC {
         FMC {
             fmc: self,
-            hclk: FMC_PER::clock(clocks),
+            hclk: <FMC_PER as RccBus>::Bus::clock(clocks),
         }
     }
 }

src/fmpi2c.rs

@@ -1,10 +1,8 @@
-use core::ops::Deref;
-
 use crate::gpio;
 
 use crate::pac::fmpi2c1 as i2c1;
 use crate::pac::{self, rcc};
-use crate::rcc::{BusClock, Enable, Rcc, Reset};
+use crate::rcc::{BusClock, Rcc};
 use fugit::{HertzU32 as Hertz, RateExtU32};
 use micromath::F32Ext;
 
@@ -25,13 +23,7 @@ mod hal_1;
 type I2cSel = rcc::dckcfgr2::FMPI2C1SEL;
 
 pub trait Instance:
-    crate::Sealed
-    + crate::Ptr<RB = i2c1::RegisterBlock>
-    + Deref<Target = Self::RB>
-    + Enable
-    + Reset
-    + BusClock
-    + gpio::alt::I2cCommon
+    crate::rcc::Instance + crate::Ptr<RB = i2c1::RegisterBlock> + gpio::alt::I2cCommon
 {
     fn set_clock_source(rcc: &rcc::RegisterBlock, source: I2cSel);
 }
@@ -291,7 +283,7 @@ impl<I2C: Instance> I2c<I2C> {
         let i2c_timingr = match clocks {
             ClockSource::Apb => {
                 I2C::set_clock_source(rcc, I2cSel::Apb);
-                let pclk = I2C::clock(&rcc.clocks);
+                let pclk = I2C::Bus::clock(&rcc.clocks);
                 match mode {
                     Mode::Standard { frequency } => {
                         calculate_timing(I2C_STANDARD_MODE_SPEC, pclk, frequency, an_filter, dnf)

src/i2c.rs

@@ -1,7 +1,4 @@
-use core::ops::Deref;
-
 use crate::pac::{self, i2c1};
-use crate::rcc::{Enable, Reset};
 
 use crate::gpio;
 
@@ -75,12 +72,7 @@ pub struct I2c<I2C: Instance> {
 }
 
 pub trait Instance:
-    crate::Sealed
-    + crate::Ptr<RB = i2c1::RegisterBlock>
-    + Deref<Target = Self::RB>
-    + Enable
-    + Reset
-    + gpio::alt::I2cCommon
+    crate::rcc::Instance + crate::Ptr<RB = i2c1::RegisterBlock> + gpio::alt::I2cCommon
 {
 }
 

src/i2s.rs

@@ -23,7 +23,11 @@ pub extern crate stm32_i2s_v12x;
 
 /// Trait for SPI peripheral with i2s capability.
 pub trait Instance:
-    I2sFreq + rcc::Enable + rcc::Reset + gpio::alt::I2sCommon + gpio::alt::I2sMaster
+    rcc::Instance
+    + crate::Ptr<RB = pac::spi1::RegisterBlock>
+    + rcc::RccBus<Bus: I2sFreq>
+    + gpio::alt::I2sCommon
+    + gpio::alt::I2sMaster
 {
 }
 
@@ -41,16 +45,6 @@ pub trait I2sFreq {
     }
 }
 
-impl<T> I2sFreq for T
-where
-    T: rcc::RccBus,
-    T::Bus: I2sFreq,
-{
-    fn try_i2s_freq(clocks: &Clocks) -> Option<Hertz> {
-        T::Bus::try_i2s_freq(clocks)
-    }
-}
-
 impl I2sFreq for rcc::APB1 {
     fn try_i2s_freq(clocks: &Clocks) -> Option<Hertz> {
         #[cfg(not(feature = "rcc_i2s_apb"))]
@@ -173,7 +167,7 @@ impl<SPI: Instance> I2s<SPI> {
         ),
         rcc: &mut Rcc,
     ) -> Self {
-        let input_clock = SPI::i2s_freq(&rcc.clocks);
+        let input_clock = SPI::Bus::i2s_freq(&rcc.clocks);
         // Enable clock, enable reset, clear, reset
         SPI::enable(rcc);
         SPI::reset(rcc);
@@ -319,7 +313,7 @@ impl<SPI: DualInstance> DualI2s<SPI> {
         ),
         rcc: &mut Rcc,
     ) -> Self {
-        let input_clock = SPI::i2s_freq(&rcc.clocks);
+        let input_clock = SPI::Bus::i2s_freq(&rcc.clocks);
         // Enable clock, enable reset, clear, reset
         // Note: this also affect the I2SEXT peripheral
         SPI::enable(rcc);
@@ -458,7 +452,6 @@ mod dma {
     use crate::dma::traits::{DMASet, PeriAddress};
     use crate::pac::spi1::RegisterBlock;
     use core::marker::PhantomData;
-    use core::ops::Deref;
     use stm32_i2s_v12x::driver::{I2sCore, I2sDriver};
     use stm32_i2s_v12x::transfer::{Ext, Main};
     use stm32_i2s_v12x::DualI2sPeripheral;
@@ -467,7 +460,6 @@ mod dma {
     unsafe impl<SPI: Instance, MS, TR, STD> PeriAddress for I2sDriver<I2s<SPI>, MS, TR, STD>
     where
         I2s<SPI>: stm32_i2s_v12x::I2sPeripheral,
-        SPI: Deref<Target = crate::pac::spi1::RegisterBlock>,
     {
         /// SPI_DR is only 16 bits. Multiple transfers are needed for a 24-bit or 32-bit sample,
         /// as explained in the reference manual.

src/qei.rs

@@ -97,7 +97,7 @@ impl<TIM: Instance> embedded_hal_02::Qei for Qei<TIM> {
     }
 }
 
-pub trait Instance: crate::Sealed + rcc::Enable + rcc::Reset + General + CPin<0> + CPin<1> {
+pub trait Instance: rcc::Instance + General + CPin<0> + CPin<1> {
     fn setup_qei(&mut self);
 
     fn read_direction(&self) -> bool;

src/rcc/f4/enable.rs

@@ -69,6 +69,7 @@ macro_rules! bus_reset {
 macro_rules! bus {
     ($($PER:ident => ($busX:ty, $bit:literal),)+) => {
         $(
+            impl crate::rcc::Instance for crate::pac::$PER {}
             impl RccBus for crate::pac::$PER {
                 type Bus = $busX;
             }
@@ -79,6 +80,8 @@ macro_rules! bus {
     }
 }
 
+#[cfg(feature = "quadspi")]
+impl crate::rcc::Instance for crate::pac::QUADSPI {}
 #[cfg(feature = "quadspi")]
 impl RccBus for crate::pac::QUADSPI {
     type Bus = AHB3;
@@ -144,6 +147,8 @@ bus! {
     FMC => (AHB3, 0),
 }
 
+#[cfg(feature = "fsmc")]
+impl crate::rcc::Instance for crate::pac::FSMC {}
 // TODO: fix absent ahb3lpenr
 #[cfg(feature = "fsmc")]
 impl RccBus for crate::pac::FSMC {
@@ -246,6 +251,8 @@ bus! {
     ADC1 => (APB2, 8),
 }
 
+#[cfg(feature = "adc2")]
+impl crate::rcc::Instance for crate::pac::ADC2 {}
 #[cfg(feature = "adc2")]
 impl RccBus for crate::pac::ADC2 {
     type Bus = APB2;
@@ -257,6 +264,8 @@ bus_lpenable!(ADC2 => 9);
 #[cfg(feature = "adc2")]
 bus_reset!(ADC2 => 8);
 
+#[cfg(feature = "adc3")]
+impl crate::rcc::Instance for crate::pac::ADC3 {}
 #[cfg(feature = "adc3")]
 impl RccBus for crate::pac::ADC3 {
     type Bus = APB2;

src/rcc/mod.rs

@@ -88,6 +88,12 @@ impl RccExt for RCC {
     }
 }
 
+/// Common trait for most of peripherals
+pub trait Instance:
+    crate::Ptr + crate::Steal + Enable + Reset + RccBus<Bus: BusClock> + Deref<Target = Self::RB>
+{
+}
+
 /// Bus associated to peripheral
 pub trait RccBus: crate::Sealed {
     /// Bus type;
@@ -106,26 +112,6 @@ pub trait BusTimerClock {
     fn timer_clock(clocks: &Clocks) -> Hertz;
 }
 
-impl<T> BusClock for T
-where
-    T: RccBus,
-    T::Bus: BusClock,
-{
-    fn clock(clocks: &Clocks) -> Hertz {
-        T::Bus::clock(clocks)
-    }
-}
-
-impl<T> BusTimerClock for T
-where
-    T: RccBus,
-    T::Bus: BusTimerClock,
-{
-    fn timer_clock(clocks: &Clocks) -> Hertz {
-        T::Bus::timer_clock(clocks)
-    }
-}
-
 /// Enable/disable peripheral
 pub trait Enable: RccBus {
     /// Enables peripheral

src/sai.rs

@@ -220,16 +220,7 @@ pub struct Receive;
 /// SAI sub-block which has been configured as a transmitter.
 pub struct Transmit;
 
-pub trait Instance:
-    crate::Sealed
-    + crate::Ptr<RB = sai::RegisterBlock>
-    + crate::Steal
-    + Deref<Target = Self::RB>
-    + rcc::Enable
-    + rcc::Reset
-    + rcc::BusClock
-{
-}
+pub trait Instance: rcc::Instance + crate::Ptr<RB = sai::RegisterBlock> {}
 
 impl<SAI: Instance, const C: bool> SAICH<SAI, C> {
     fn new(sai: SAI) -> Self {

src/serial.rs

@@ -14,6 +14,7 @@
 //! the embedded-hal read and write traits with `u16` as the word type. You can use these
 //! implementations for 9-bit words.
 
+use crate::rcc::BusClock;
 use core::fmt;
 use core::marker::PhantomData;
 use enumflags2::BitFlags;
@@ -126,16 +127,7 @@ pub use config::Config;
 pub use gpio::alt::SerialAsync as CommonPins;
 
 // Implemented by all USART/UART instances
-pub trait Instance:
-    crate::Sealed
-    + crate::Ptr<RB: RegisterBlockImpl>
-    + crate::Steal
-    + core::ops::Deref<Target = Self::RB>
-    + rcc::Enable
-    + rcc::Reset
-    + rcc::BusClock
-    + CommonPins
-{
+pub trait Instance: rcc::Instance + crate::Ptr<RB: RegisterBlockImpl> + CommonPins {
     #[doc(hidden)]
     #[inline(always)]
     fn peri_address() -> u32 {
@@ -265,7 +257,7 @@ impl<USART: Instance, WORD> Serial<USART, WORD> {
         USART::enable(rcc);
         USART::reset(rcc);
 
-        let pclk_freq = USART::clock(&rcc.clocks).raw();
+        let pclk_freq = USART::Bus::clock(&rcc.clocks).raw();
         let baud = config.baudrate.0;
 
         if !USART::RB::IRDA && config.irda != IrdaMode::None {

src/spi.rs

@@ -1,3 +1,4 @@
+use crate::rcc::BusClock;
 use core::marker::PhantomData;
 use core::ops::{Deref, DerefMut};
 
@@ -210,13 +211,7 @@ impl<SPI: Instance, const BIDI: bool, W> DerefMut for SpiSlave<SPI, BIDI, W> {
 
 // Implemented by all SPI instances
 pub trait Instance:
-    crate::Sealed
-    + crate::Ptr<RB = spi1::RegisterBlock>
-    + Deref<Target = Self::RB>
-    + rcc::Enable
-    + rcc::Reset
-    + rcc::BusClock
-    + gpio::alt::SpiCommon
+    rcc::Instance + crate::Ptr<RB = spi1::RegisterBlock> + gpio::alt::SpiCommon
 {
 }
 
@@ -488,7 +483,7 @@ impl<SPI: Instance> Spi<SPI, false, u8> {
         );
 
         Self::_new(spi, pins)
-            .pre_init(mode.into(), freq, SPI::clock(&rcc.clocks))
+            .pre_init(mode.into(), freq, SPI::Bus::clock(&rcc.clocks))
             .init()
     }
 }
@@ -512,7 +507,7 @@ impl<SPI: Instance> Spi<SPI, true, u8> {
         let pins = (pins.0, SPI::NoMiso, pins.1);
 
         Self::_new(spi, pins)
-            .pre_init(mode.into(), freq, SPI::clock(&rcc.clocks))
+            .pre_init(mode.into(), freq, SPI::Bus::clock(&rcc.clocks))
             .init()
     }
 }