Fixup formatting

stm32-rs · Feb 12, 2023 · c08d39f · c08d39f
1 parent e434620
commit c08d39f
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Showing 2 changed files with 15 additions and 16 deletions.
diff --git a/src/fdcan/interrupt.rs b/src/fdcan/interrupt.rs
@@ -197,6 +197,9 @@ mod tests {
 
         let mut ints = Interrupts::RX_FIFO_0_FULL;
         ints |= Interrupt::RxFifo1Full;
-        assert_eq!(ints, Interrupts::RX_FIFO_0_FULL | Interrupts::RX_FIFO_1_FULL);
+        assert_eq!(
+            ints,
+            Interrupts::RX_FIFO_0_FULL | Interrupts::RX_FIFO_1_FULL
+        );
     }
 }
diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs
@@ -180,17 +180,17 @@ impl Rcc {
         let pll_freq = pll_input_freq / pll_cfg.m.divisor() * pll_cfg.n.multiplier();
 
         // Calculate the output frequencies for the P, Q, and R outputs
-        let p = pll_cfg.p.map(|p| {
-            ((pll_freq / p.divisor()).hz(), p.register_setting())
-        });
+        let p = pll_cfg
+            .p
+            .map(|p| ((pll_freq / p.divisor()).hz(), p.register_setting()));
 
-        let q = pll_cfg.q.map(|q| {
-            ((pll_freq / q.divisor()).hz(), q.register_setting())
-        });
+        let q = pll_cfg
+            .q
+            .map(|q| ((pll_freq / q.divisor()).hz(), q.register_setting()));
 
-        let r = pll_cfg.r.map(|r| {
-            ((pll_freq / r.divisor()).hz(), r.register_setting())
-        });
+        let r = pll_cfg
+            .r
+            .map(|r| ((pll_freq / r.divisor()).hz(), r.register_setting()));
 
         // Set the M input divider, the N multiplier for the PLL, and the PLL source.
         self.rb.pllcfgr.modify(|_, w| unsafe {
@@ -213,17 +213,13 @@ impl Rcc {
 
             // Set and enable Q if requested
             let w = match q {
-                Some((_, register_setting)) => {
-                    w.pllq().bits(register_setting).pllqen().set_bit()
-                }
+                Some((_, register_setting)) => w.pllq().bits(register_setting).pllqen().set_bit(),
                 None => w,
             };
 
             // Set and enable R if requested
             let w = match r {
-                Some((_, register_setting)) => {
-                    w.pllr().bits(register_setting).pllren().set_bit()
-                }
+                Some((_, register_setting)) => w.pllr().bits(register_setting).pllren().set_bit(),
                 None => w,
             };