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Fix #34 #40

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Dec 13, 2021
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2 changes: 2 additions & 0 deletions src/fdcan.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1391,6 +1391,7 @@ where
// Check if there is a request pending to abort
if self.has_pending_frame(idx) {
let idx: u8 = idx.into();
let idx = 1u8 << idx;

// Abort Request
can.txbcr.write(|w| unsafe { w.cr().bits(idx) });
Expand All @@ -1411,6 +1412,7 @@ where
fn has_pending_frame(&self, idx: Mailbox) -> bool {
let can = self.registers();
let idx: u8 = idx.into();
let idx = 1u8 << idx;

can.txbrp.read().trp().bits() & idx != 0
}
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4 changes: 2 additions & 2 deletions src/fdcan/filter.rs
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ impl StandardFilter {
filter: 0x0,
mask: 0x0,
},
action: Action::StoreInFifo0,
action: Action::StoreInFifo1,
}
}

Expand Down Expand Up @@ -80,7 +80,7 @@ impl ExtendedFilter {
filter: 0x0,
mask: 0x0,
},
action: Action::StoreInFifo0,
action: Action::StoreInFifo1,
}
}

Expand Down
2 changes: 1 addition & 1 deletion src/fdcan/message_ram/txbuffer_element.rs
Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@ impl<'a> ID_W<'a> {
#[inline(always)]
#[allow(dead_code)]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
self.w.bits[0] = (self.w.bits[0] & !(0x0FFFFFFF)) | ((value as u32) & 0x0FFFFFFF);
self.w.bits[0] = (self.w.bits[0] & !(0x1FFFFFFF)) | ((value as u32) & 0x1FFFFFFF);
self.w
}
}
Expand Down