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Tidy cargo doc warnings, fix links in rcc
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richardeoin committed Jan 20, 2024

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1 parent cd7c125 commit 88afbd8
Showing 6 changed files with 18 additions and 20 deletions.
4 changes: 2 additions & 2 deletions src/adc.rs
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@@ -1,7 +1,7 @@
//! Analog to Digital Converter (ADC)
//!
//! ADC1 and ADC2 share a reset line. To initialise both of them, use the
//! [`adc12`](adc12) method.
//! [`adc12`] method.
//!
//! # Examples
//!
@@ -999,7 +999,7 @@ macro_rules! adc_hal {

/// Set ADC sampling time
///
/// Options can be found in [AdcSampleTime](crate::adc::AdcSampleTime).
/// Options can be found in [AdcSampleTime].
pub fn set_sample_time(&mut self, t_samp: AdcSampleTime) {
self.sample_time = t_samp;
}
11 changes: 5 additions & 6 deletions src/delay.rs
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@@ -1,11 +1,10 @@
//! Delay providers
//!
//! There are currently two delay providers. In general you should prefer to use
//! [Delay](Delay), however if you do not have access to `SYST` you can use
//! [DelayFromCountDownTimer](DelayFromCountDownTimer) with any timer that
//! implements the [CountDown](embedded_hal::timer::CountDown) trait. This can be
//! useful if you're using [RTIC](https://rtic.rs)'s schedule API, which occupies
//! the `SYST` peripheral.
//! [Delay], however if you do not have access to `SYST` you can use
//! [DelayFromCountDownTimer] with any timer that implements the [CountDown]
//! trait. This can be useful if you're using [RTIC](https://rtic.rs)'s schedule
//! API, which occupies the `SYST` peripheral.
//!
//! # Examples
//!
@@ -68,7 +67,7 @@ pub struct Delay {
syst: SYST,
}

/// Implements [CountDown](embedded_hal::timer::CountDown) for the System timer (SysTick).
/// Implements [CountDown] for the System timer (SysTick).
pub struct Countdown<'a> {
clocks: CoreClocks,
syst: &'a mut SYST,
8 changes: 4 additions & 4 deletions src/dma/mdma.rs
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@@ -44,10 +44,10 @@
//! Unlike DMA1/DMA2, it is valid to assign the same request line to multiple
//! MDMA streams. Additionally there are multiple requests lines to choose from
//! for each target peripheral. For this reason, hardware request lines are
//! specified as part of the [`MdmaConfig`](MdmaConfig) instead of being
//! inferred from the peripheral type. If no hardware request line is specified,
//! then the request line originates from software and the transfer is started
//! immediately when [`enable`](Stream0#method.enable) is called.
//! specified as part of the [`MdmaConfig`] instead of being inferred from the
//! peripheral type. If no hardware request line is specified, then the request
//! line originates from software and the transfer is started immediately when
//! [`enable`](Stream0#method.enable) is called.
//!
//!
4 changes: 2 additions & 2 deletions src/dma/mod.rs
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@@ -19,14 +19,14 @@
//!
//! The following table summarizes the available DMA controllers
//!
//! | Controller | Accessible Memories | Peripheral [TargetAddress](traits::TargetAddress) Implementations | Double Buffering Supported ? | Number of DMA Streams | Initialization Method
//! | Controller | Accessible Memories | Peripheral [TargetAddress] Implementations | Double Buffering Supported ? | Number of DMA Streams | Initialization Method
//! | --- | --- | --- | --- | --- | ---
//! | [MDMA](mdma) | All | `QUADSPI`, .. | No |16| [Transfer::init_master](Transfer#method.init_master)
//! | [DMA1](dma) | AXISRAM, SRAM1/2/3/4 | all others [^notimpl] | Yes |8| [Transfer::init](Transfer#method.init)
//! | [DMA2](dma) | AXISRAM, SRAM1/2/3/4 | all others [^notimpl] | Yes |8| [Transfer::init](Transfer#method.init)
//! | [BDMA](bdma) | SRAM4 [^rm0455bdma] | `LPUART1`, `SPI6`, `I2C4`, `SAI4` | Yes |8| [Transfer::init](Transfer#method.init)
//!
//! [^notimpl]: [TargetAddress](traits::TargetAddress) is not yet implemented
//! [^notimpl]: [TargetAddress] is not yet implemented
//! for many peripherals
//!
//! [^rm0455bdma]: On 7B3/7A3/7B0 parts there are two BDMA controllers. BDMA1
2 changes: 1 addition & 1 deletion src/lib.rs
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@@ -46,7 +46,7 @@
//!
//! * [Direct Memory Access (DMA)](crate::dma)
//! * [Cyclic Redundancy Check (CRC)](crate::crc) Feature gate `crc`
//! * [Random Number Generator](crate::rng) ([rand_core::RngCore](rand_core::RngCore) is implemented under the `rand` feature gate)
//! * [Random Number Generator](crate::rng) ([rand_core::RngCore] is implemented under the `rand` feature gate)
//! * [Embedded Flash Memory](crate::flash)
//! * [System Window Watchdog](crate::system_watchdog)
//! * [Independent Watchdog](crate::independent_watchdog)
9 changes: 4 additions & 5 deletions src/rcc/mod.rs
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@@ -108,10 +108,9 @@
//! # Peripherals
//!
//! The `freeze()` method returns a [Core Clocks Distribution and Reset
//! (CCDR)](struct.Ccdr.html) object. This singleton tells you how the core
//! clocks were actually configured (in [CoreClocks](struct.CoreClocks.html))
//! and allows you to configure the remaining peripherals (see
//! [PeripheralREC](crate::rcc::rec::struct.PeripheralREC.html)).
//! (CCDR)](Ccdr) object. This singleton tells you how the core clocks were
//! actually configured (in [CoreClocks]) and allows you to configure the
//! remaining peripherals (see [PeripheralREC]).
//!
//!```rust
//! let ccdr = ...; // Returned by `freeze()`, see examples above
@@ -126,7 +125,7 @@
//! ccdr.peripheral.FDCAN.enable().reset();
//!```
//!
//! The [PeripheralREC](struct.PeripheralREC.html) members implement move
//! The [PeripheralREC] members implement move
//! semantics, so once you have passed them to a constructor they cannot be
//! modified again in safe Rust.
//!

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