Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix "log" feature flag for RM0455 parts, expand CI to cover this path #496

Merged
merged 1 commit into from
May 12, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 5 additions & 4 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,9 @@ jobs:
- stm32h7b3
- stm32h7b0
- stm32h735
env: # Peripheral Feature flags
FLAGS: rt,xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi,defmt
env:
FLAGS: rt,defmt,log
PERIPHERAL: xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi

steps:
- uses: actions/checkout@v4
Expand All @@ -53,5 +54,5 @@ jobs:
with:
toolchain: ${{ matrix.rust }}
targets: thumbv7em-none-eabihf
- run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }}
- run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }}
- run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}
- run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}
9 changes: 5 additions & 4 deletions .github/workflows/nightly.yml
Original file line number Diff line number Diff line change
Expand Up @@ -18,8 +18,9 @@ jobs:
- log-itm
- log-semihost
- log-rtt
env: # Peripheral Feature flags
FLAGS: rt,xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi
env:
FLAGS: rt,log
PERIPHERAL: xspi,sdmmc,sdmmc-fatfs,fmc,usb_hs,rtc,ethernet,ltdc,crc,rand,can,dsi

steps:
- uses: actions/checkout@v4
Expand All @@ -38,5 +39,5 @@ jobs:
- uses: dtolnay/rust-toolchain@nightly
with:
targets: thumbv7em-none-eabihf
- run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ matrix.logging }}
- run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }}
- run: cargo build --verbose --release --examples --target thumbv7em-none-eabihf --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }},${{ matrix.logging }}
- run: cargo test --lib --target x86_64-unknown-linux-gnu --features ${{ matrix.mcu }},${{ env.FLAGS }},${{ env.PERIPHERAL }}
66 changes: 46 additions & 20 deletions src/rcc/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -985,26 +985,52 @@ impl Rcc {
cfgr.sws().variant().unwrap()
);

let d1cfgr = rcc.d1cfgr.read();
debug!(
"D1CFGR register: D1CPRE={:?} HPRE={:?} D1PPRE={:?}",
d1cfgr.d1cpre().variant().unwrap(),
d1cfgr.hpre().variant().unwrap(),
d1cfgr.d1ppre().variant().unwrap(),
);

let d2cfgr = rcc.d2cfgr.read();
debug!(
"D2CFGR register: D2PPRE1={:?} D2PPRE1={:?}",
d2cfgr.d2ppre1().variant().unwrap(),
d2cfgr.d2ppre2().variant().unwrap(),
);

let d3cfgr = rcc.d3cfgr.read();
debug!(
"D3CFGR register: D3PPRE={:?}",
d3cfgr.d3ppre().variant().unwrap(),
);
#[cfg(not(feature = "rm0455"))]
{
let d1cfgr = rcc.d1cfgr.read();
debug!(
"D1CFGR register: D1CPRE={:?} HPRE={:?} D1PPRE={:?}",
d1cfgr.d1cpre().variant().unwrap(),
d1cfgr.hpre().variant().unwrap(),
d1cfgr.d1ppre().variant().unwrap(),
);

let d2cfgr = rcc.d2cfgr.read();
debug!(
"D2CFGR register: D2PPRE1={:?} D2PPRE1={:?}",
d2cfgr.d2ppre1().variant().unwrap(),
d2cfgr.d2ppre2().variant().unwrap(),
);

let d3cfgr = rcc.d3cfgr.read();
debug!(
"D3CFGR register: D3PPRE={:?}",
d3cfgr.d3ppre().variant().unwrap(),
);
}
#[cfg(feature = "rm0455")]
{
let cdcfgr1 = rcc.cdcfgr1.read();
debug!(
"CDCFGR1 register: CDCPRE={:?} HPRE={:?} CDPPRE={:?}",
cdcfgr1.cdcpre().variant().unwrap(),
cdcfgr1.hpre().variant().unwrap(),
cdcfgr1.cdppre().variant().unwrap(),
);

let cdcfgr2 = rcc.cdcfgr2.read();
debug!(
"CDCFGR2 register: CDPPRE1={:?} CDPPRE1={:?}",
cdcfgr2.cdppre1().variant().unwrap(),
cdcfgr2.cdppre2().variant().unwrap(),
);

let srdcfgr = rcc.srdcfgr.read();
debug!(
"SRDCFGR register: SRDPPRE={:?}",
srdcfgr.srdppre().bits(),
);
}

let pllckselr = rcc.pllckselr.read();
debug!(
Expand Down
Loading