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Tidying up clock config of H5. #2695
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Ah, I'm stupid. |
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Hi @dojyorin |
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@fpistm |
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For example, by organizing things in this PR, it will be easier to visually distinguish the differences in a diff editor, making it easier to add new variants and apply patches. I'm currently developing several custom H5 boards, and when I was referencing the code of existing variants to add a variant, I was a little confused by the subtle variations in numbers and notation. I submitted a PR to reduce experiences like this. |
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@fpistm I'll fix the corrections this weekend. |
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Honestly, I understand your point to change config order will help ton compare anyway changing several values just to have less difference is risky and probably add regressions.
Current config is know to work and I have no time to test this PR on each target to ensure it is correct.
Please revert to CSI the Nucleo H503RB config as the one you set is not correct.
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I thought I had checked datasheets, but it seems I still didn't fully understand it. |
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I've updated the PR. Honestly, anytime a new H5 board will be added the clock config will not be aligned with your reordering. |
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LGTM. No test performed.
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I understood that code cleanup does not make much sense. |
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Not agreed. I understand your point about diff but you changed some configurations for specific hardware which could bring some regressions. And as stated above cube mx does not follow this rules. Anyway any contributions are welcome. I'd like to have more contributions and hope to find new maintainers. Moreover some of your changes seems go to have a better configurations. 😉 |
Signed-off-by: dojyorin <ota_droid@live.jp>
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Summary
The generic clock config for STM32H5 series will be made as common as possible.
As a result, only differences will be the number of peripherals that vary by part number, clock source and peripherals used by each variant, etc.
We have also tidied up the writing style, such as commenting out.
This fixes
H503KBUwhich was not included in #2598 fix.Common changes
USBusesHSI48H503RCC_PERIPHCLK_ADCDACRCC_PERIPHCLK_LPUART1RCC_PERIPHCLK_USBRCC_PERIPHCLK_SPI1RCC_PERIPHCLK_SPI2RCC_PERIPHCLK_SPI3H562H563H573SDMMC1operates at 50MHz.RCC_PERIPHCLK_SDMMC1RCC_PERIPHCLK_ADCDACRCC_PERIPHCLK_LPUART1RCC_PERIPHCLK_USBRCC_PERIPHCLK_SPI1RCC_PERIPHCLK_SPI2RCC_PERIPHCLK_SPI3RCC_PERIPHCLK_SPI4RCC_PERIPHCLK_SPI5RCC_PERIPHCLK_SPI6RCC_PERIPHCLK_SPI4andRCC_PERIPHCLK_SPI5is only for models with high pin count.Variant-specific changes
H503CB(T-U)H503KBUPLL1Qvalue has been made consistent withH503CB(T-U)andH503RBTvalues.H503RBTNUCLEO_H503RBH503RBT.H562R(G-I)TPLL2RandUSBvalue has been made consistent withH563R(G-I)T,H563IIKxQ_H573IIKxQandH563Z(G-I)Tvalues.WEACT_H562RGH562R(G-I)T.H563IIKxQ_H573IIKxQOSPIremoved.STM32H573I_DKH563IIKxQ_H573IIKxQ.SAIis enabled, I have not touchedPLL2multiplex.H563R(G-I)TPLL2RandSDMMC1value has been made consistent withH562R(G-I)T,H563IIKxQ_H573IIKxQandH563Z(G-I)Tvalues.H563Z(G-I)TSDMMC1value has been made consistent withH562R(G-I)T,H563IIKxQ_H573IIKxQandH563R(G-I)Tvalues.NUCLEO_H563ZIH563Z(G-I)T.H563Z(G-I)T.