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perf: remove 15 cols from poseidon2 wide (#1397)
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9 changes: 7 additions & 2 deletions
9
crates/recursion/core-v2/src/chips/poseidon2_wide/columns/preprocessed.rs
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,9 +1,14 @@ | ||
use sp1_derive::AlignedBorrow; | ||
|
||
use crate::chips::{mem::MemoryAccessCols, poseidon2_wide::WIDTH}; | ||
use crate::{ | ||
chips::{mem::MemoryAccessCols, poseidon2_wide::WIDTH}, | ||
Address, | ||
}; | ||
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||
#[derive(AlignedBorrow, Clone, Copy, Debug)] | ||
#[repr(C)] | ||
pub struct Poseidon2PreprocessedCols<T: Copy> { | ||
pub memory_preprocessed: [MemoryAccessCols<T>; 2 * WIDTH], | ||
pub input: [Address<T>; WIDTH], | ||
pub output: [MemoryAccessCols<T>; WIDTH], | ||
pub is_real_neg: T, | ||
} |
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