Add the instruction c.ebreak

src/emulate.c

@@ -148,6 +148,37 @@ static void rv_except_illegal_insn(struct riscv_t *rv, uint32_t insn)
     rv->csr_mcause = code;
 }
 
+void rv_except_breakpoint(struct riscv_t *rv)
+{
+    /* mtvec (Machine Trap-Vector Base Address Register)
+     * mtvec[MXLEN-1:2]: vector base address
+     * mtvec[1:0] : vector mode
+     */
+    const uint32_t base = rv->csr_mtvec & ~0x3;
+    const uint32_t mode = rv->csr_mtvec & 0x3;
+
+    /* Exception Code: Breakpoint */
+    const uint32_t code = 3;
+
+    /* mepc (Machine Exception Program Counter)
+     * mtval(Machine Trap Value Register) : Breakpoint
+     */
+    rv->csr_mepc = rv->PC;
+    rv->csr_mtval = rv->PC;
+
+    switch (mode) {
+    case 0: /* DIRECT: All exceptions set PC to base */
+        rv->PC = base;
+        break;
+    case 1: /* VECTORED: Asynchronous interrupts set PC to base + 4 * code */
+        rv->PC = base + 4 * code;
+        break;
+    }
+
+    /* mcause (Machine Cause Register): store exception code */
+    rv->csr_mcause = code;
+}
+
 /* RV32I Base Instruction Set
  *
  * bits  0-6:  opcode

src/main.c

@@ -186,7 +186,7 @@ int main(int argc, char **args)
 
         /* system */
         .on_ecall = syscall_handler,
-        .on_ebreak = rv_halt,
+        .on_ebreak = rv_except_breakpoint,
     };
 
     state_t *state = state_new();

src/riscv.h

@@ -125,6 +125,9 @@ riscv_word_t rv_get_reg(struct riscv_t *, uint32_t reg);
 /* system call handler */
 void syscall_handler(struct riscv_t *rv);
 
+/* trigger a breakpoint exception */
+void rv_except_breakpoint(struct riscv_t *rv);
+
 /* halt the core */
 void rv_halt(struct riscv_t *);