Recognize more NOP encodings

The RISC-V User-Level ISA Specification defines NOP instruction as:
  The NOP instruction does not change any user-visible state, except
  for advancing the pc. NOP is encoded as "ADDI x0, x0, 0".

The spec have the following note:
  NOPs can be used to align code segments to microarchitecturally
  significant address boundaries, or to leave space for inline code
  modifications. Although there are many possible ways to encode a NOP,
  we define a canonical NOP encoding to allow microarchitectural
  optimizations as well as for more readable disassembly output.

src/decode.c

@@ -449,7 +449,9 @@ static inline bool op_op_imm(rv_insn_t *ir, const uint32_t insn)
     /* decode I-type */
     decode_itype(ir, insn);
 
-    /* nop can be implemented as "addi x0, x0, 0" */
+    /* nop can be implemented as "addi x0, x0, 0".
+     * Any integer computational instruction writing into "x0" is NOP.
+     */
     if (unlikely(ir->rd == rv_reg_zero)) {
         ir->opcode = rv_insn_nop;
         return true;
@@ -506,6 +508,12 @@ static inline bool op_auipc(rv_insn_t *ir, const uint32_t insn)
     /* decode U-type */
     decode_utype(ir, insn);
 
+    /* Any integer computational instruction writing into "x0" is NOP. */
+    if (unlikely(ir->rd == rv_reg_zero)) {
+        ir->opcode = rv_insn_nop;
+        return true;
+    }
+
     ir->opcode = rv_insn_auipc;
     return true;
 }
@@ -684,6 +692,12 @@ static inline bool op_lui(rv_insn_t *ir, const uint32_t insn)
     /* decode U-type */
     decode_utype(ir, insn);
 
+    /* Any integer computational instruction writing into "x0" is NOP. */
+    if (unlikely(ir->rd == rv_reg_zero)) {
+        ir->opcode = rv_insn_nop;
+        return true;
+    }
+
     ir->opcode = rv_insn_lui;
     return true;
 }

src/rv32_template.c

@@ -3,7 +3,6 @@
 /* Internal */
 static bool do_nop(riscv_t *rv, const rv_insn_t *ir)
 {
-    rv->X[rv_reg_zero] = 0;
     rv->csr_cycle++;
     rv->PC += ir->insn_len;
     const rv_insn_t *next = ir + 1;