Introducing register allocation for the tier-1 JIT compiler

Register allocation effectively reuses the host register value, thereby
reducing the number of load and store instructions.

Take continuous addi instructions as an example:
```
addi t0, t0, 1
addi t0, t0, 1
addi t0, t0, 1
```
* The generated machine code without register allocation
```
load t0, t0_addr
add t0, 1
sw t0, t0_addr
load t0, t0_addr
add t0, 1
sw t0, t0_addr
load t0, t0_addr
add t0, 1
sw t0, t0_addr
```
* The generated machine code without register allocation
```
load t0, t0_addr
add t0, 1
add t0, 1
add t0, 1
sw t0, t0_addr
```
As shown in the above example, register allocation reuses the host
register and reduces the number of load and store instructions.

| Metric   | With RA  |  W/O RA  | SpeedUp |
|----------+----------+----------+---------|
| dhrystone| 0.342 s  | 0.328 s  |  +4.27% |
| miniz    | 1.243 s  | 1.185 s  |  +4.89% |
| primes   | 1.716 s  | 1.689 s  |  +1.60% |
| sha512   | 2.063 s  | 1.880 s  |  +9.73% |
| stream   |11.619 s  |11.419 s  |  +1.75% |

As demonstrated in the performance analysis, the register allocation
improves the overall performance for the T1C generated machine code.