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Update README with full F Extension Support
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@visitorckw
visitorckw committed Nov 11, 2023
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Expand Up @@ -24,8 +24,7 @@ a focus on efficiency and readability.

Features:
* Fast interpreter for executing the RV32 ISA
* Comprehensive support for RV32I and M, A, C extensions
* Partial support for the F extension
* Comprehensive support for RV32I and M, A, C, F extensions
* Memory-efficient design
* Built-in ELF loader
* Implementation of commonly used newlib system calls
Expand Down Expand Up @@ -143,7 +142,6 @@ Current progress of this emulator in riscv-arch-test (RV32):
- `C`: Standard Extension for Compressed Instruction
- `Zifencei`: Instruction-Fetch Fence
- `privilege`: RISCV Privileged Specification
* Unsupported tests (runnable but incomplete)
- `F` Standard Extension for Single-Precision Floating-Point

Detail in riscv-arch-test:
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1 comment on commit d31e18c

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@jserv jserv commented on d31e18c Nov 11, 2023

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Benchmarks

Benchmark suite Current: d31e18c Previous: 84f93ac Ratio
Dhrystone 1740 Average DMIPS over 10 runs 1679 Average DMIPS over 10 runs 0.96
Coremark 1474.369 Average iterations/sec over 10 runs 1485.616 Average iterations/sec over 10 runs 1.01

This comment was automatically generated by workflow using github-action-benchmark.

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