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Rollback partial wrong implemented code in pr #89 #114

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merged 3 commits into from
Feb 19, 2023
Merged

Rollback partial wrong implemented code in pr #89 #114

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df1e6fe
Edit pointer incremental according to CodeQL analysis
EagleTw Feb 13, 2023
f523c76
Merge branch 'sysprog21:master' into master
EagleTw Feb 19, 2023
2da9dd7
Change datatype of csr_cycle from uint64_t into uint32_t array
EagleTw Feb 19, 2023
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8 changes: 5 additions & 3 deletions src/emulate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,9 @@ static inline void update_time(riscv_t *rv)
struct timeval tv;
rv_gettimeofday(&tv);

rv->csr_time = (uint64_t) tv.tv_sec * 1e6 + (uint32_t) tv.tv_usec;
uint64_t t = (uint64_t) tv.tv_sec * 1e6 + (uint32_t) tv.tv_usec;
rv->csr_time[0] = t & 0xFFFFFFFF;
rv->csr_time[1] = t >> 32;
}

#if RV32_HAS(Zicsr)
Expand Down Expand Up @@ -132,11 +134,11 @@ static uint32_t *csr_get_ptr(riscv_t *rv, uint32_t csr)
/* TIME/TIMEH - very roughly about 1 ms per tick */
case CSR_TIME: { /* Timer for RDTIME instruction */
update_time(rv);
return (uint32_t *) (&rv->csr_time) + 0;
return &rv->csr_time[0];
}
case CSR_TIMEH: { /* Upper 32 bits of time */
update_time(rv);
return (uint32_t *) (&rv->csr_time + 4);
return &rv->csr_time[1];
}
case CSR_INSTRET: /* Number of Instructions Retired Counter */
/* Number of Instructions Retired Counter, just use cycle */
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2 changes: 1 addition & 1 deletion src/riscv_private.h
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ struct riscv_internal {

/* csr registers */
uint64_t csr_cycle;
uint64_t csr_time;
uint32_t csr_time[2];
uint32_t csr_mstatus;
uint32_t csr_mtvec;
uint32_t csr_misa;
Expand Down