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Remove tailcall member in rv_insn_t #245

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merged 1 commit into from
Oct 11, 2023
Merged

Remove tailcall member in rv_insn_t #245

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13 changes: 6 additions & 7 deletions src/decode.h
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Original file line number Diff line number Diff line change
Expand Up @@ -283,14 +283,14 @@ typedef struct rv_insn {
* optimization enables the self-recursive function to reuse the same
* function stack frame.
*
* The @tailcall member indicates whether an intermediate representation
* (IR) is the final instruction in a basic block. The @impl member
* facilitates the direct invocation of the next instruction emulation
* without the need to compute the jump address. By utilizing these two
* members, all instruction emulations can be rewritten into a
* The @next member indicates the next intermediate representation
* (IR) or is NULL if it is the final instruction in a basic block. The
* @impl member facilitates the direct invocation of the next instruction
* emulation without the need to compute the jump address. By utilizing
* these two members, all instruction emulations can be rewritten into a
* self-recursive version, enabling the compiler to leverage TCO.
*/
bool tailcall;
struct rv_insn *next;
bool (*impl)(riscv_t *, const struct rv_insn *);

/* Two pointers, 'branch_taken' and 'branch_untaken', are employed to
Expand All @@ -302,7 +302,6 @@ typedef struct rv_insn {
*/
struct rv_insn *branch_taken, *branch_untaken;

struct rv_insn *next;
} rv_insn_t;

/* decode the RISC-V instruction */
Expand Down
14 changes: 6 additions & 8 deletions src/emulate.c
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Original file line number Diff line number Diff line change
Expand Up @@ -356,9 +356,9 @@ enum {
};

#if RV32_HAS(GDBSTUB)
#define RVOP_NO_NEXT(ir) (ir->tailcall | rv->debug_mode)
#define RVOP_NO_NEXT(ir) (!ir->next | rv->debug_mode)
#else
#define RVOP_NO_NEXT(ir) (ir->tailcall)
#define RVOP_NO_NEXT(ir) (!ir->next)
#endif

/* record whether the branch is taken or not during emulation */
Expand Down Expand Up @@ -601,7 +601,7 @@ static void block_translate(riscv_t *rv, block_map_t *map, block_t *block)

assert(prev_ir);
block->ir_tail = prev_ir;
block->ir_tail->tailcall = true;
block->ir_tail->next = NULL;
}

#define COMBINE_MEM_OPS(RW) \
Expand All @@ -611,7 +611,7 @@ static void block_translate(riscv_t *rv, block_map_t *map, block_t *block)
if (next_ir->opcode != IIF(RW)(rv_insn_lw, rv_insn_sw)) \
break; \
count++; \
if (next_ir->tailcall) \
if (!next_ir->next) \
break; \
next_ir = next_ir->next; \
} \
Expand Down Expand Up @@ -683,7 +683,6 @@ FORCE_INLINE void remove_next_nth_ir(riscv_t *rv,
}
if (!ir->next) {
block->ir_tail = ir;
ir->tailcall = true;
}
block->n_insn -= n;
}
Expand Down Expand Up @@ -794,7 +793,6 @@ static void match_pattern(riscv_t *rv, block_t *block)
else
ir->rs1 = next_ir->rs2;
ir->impl = dispatch_table[ir->opcode];
ir->tailcall = next_ir->tailcall;
remove_next_nth_ir(rv, ir, block, 1);
}
break;
Expand All @@ -804,7 +802,7 @@ static void match_pattern(riscv_t *rv, block_t *block)
if (!IF_insn(next_ir, lui))
break;
count++;
if (next_ir->tailcall)
if (!next_ir->next)
break;
next_ir = next_ir->next;
}
Expand Down Expand Up @@ -841,7 +839,7 @@ static void match_pattern(riscv_t *rv, block_t *block)
!IF_insn(next_ir, srai))
break;
count++;
if (next_ir->tailcall)
if (!next_ir->next)
break;
next_ir = next_ir->next;
}
Expand Down