Add ACPI methods for setting fan speed

.gitmodules

@@ -1,70 +1,70 @@
 [submodule "3rdparty/blobs"]
  path = 3rdparty/blobs
- url = ../blobs.git
+ url = https://review.coreboot.org/blobs.git
  update = none
  ignore = dirty
 [submodule "util/nvidia-cbootimage"]
  path = util/nvidia/cbootimage
- url = ../nvidia-cbootimage.git
+ url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
  path = 3rdparty/vboot
- url = ../vboot.git
+ url = https://review.coreboot.org/vboot.git
  branch = main
 [submodule "arm-trusted-firmware"]
  path = 3rdparty/arm-trusted-firmware
- url = ../arm-trusted-firmware.git
+ url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
  path = 3rdparty/chromeec
- url = ../chrome-ec.git
+ url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
  path = 3rdparty/libhwbase
- url = ../libhwbase.git
+ url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
  path = 3rdparty/libgfxinit
- url = ../libgfxinit.git
+ url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
  path = 3rdparty/fsp
- url = ../fsp.git
+ url = https://review.coreboot.org/fsp.git
  update = none
  ignore = dirty
 [submodule "opensbi"]
  path = 3rdparty/opensbi
- url = ../opensbi.git
+ url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
  path = 3rdparty/intel-microcode
- url = ../intel-microcode.git
+ url = https://review.coreboot.org/intel-microcode.git
  update = none
  ignore = dirty
  branch = main
 [submodule "3rdparty/ffs"]
  path = 3rdparty/ffs
- url = ../ffs.git
+ url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
  path = 3rdparty/amd_blobs
- url = ../amd_blobs
+ url = https://review.coreboot.org/amd_blobs
  update = none
  ignore = dirty
 [submodule "3rdparty/cmocka"]
  path = 3rdparty/cmocka
- url = ../cmocka.git
+ url = https://review.coreboot.org/cmocka.git
  update = none
  branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
  path = 3rdparty/qc_blobs
- url = ../qc_blobs.git
+ url = https://review.coreboot.org/qc_blobs.git
  update = none
  ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
  path = 3rdparty/intel-sec-tools
- url = ../9esec-security-tooling.git
+ url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
  path = 3rdparty/stm
- url = ../STM
+ url = https://review.coreboot.org/STM
  branch = stmpe
 [submodule "util/goswid"]
  path = util/goswid
- url = ../goswid
+ url = https://review.coreboot.org/goswid.git
  branch = trunk
 [submodule "src/vendorcode/amd/opensil/genoa_poc/opensil"]
  path = src/vendorcode/amd/opensil/genoa_poc/opensil
- url = ../opensil_genoa_poc.git
+ url = https://review.coreboot.org/opensil_genoa_poc.git

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,38 @@
+config DRIVERS_GFX_NVIDIA
+ bool
+ default n
+ help
+ Support for NVIDIA Optimus graphics
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+ hex "PCI bridge for the GPU device"
+ default 0x01
+ depends on DRIVERS_GFX_NVIDIA
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+ depends on DRIVERS_GFX_NVIDIA
+ bool
+ default n
+ help
+ Support for NVIDIA Dynamic Boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
+ int "Total processor power offset from default TGP in watts"
+ default 45
+ depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+ help
+ This identifies the available power for the CPU or GPU boost
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN
+ int "Minimum TGP offset from default TGP in watts"
+ default 0
+ depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+ help
+ This is used to transfer power from the GPU to the CPU
+
+config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
+ int "Maximum TGP offset from default TGP in watts"
+ default 0
+ depends on DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
+ help
+ This is used to transfer power from the CPU to the GPU

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/coffeelake.asl

@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* NVIDIA GC6 on CFL and CML CPU PCIe ports */
+
+// Memory mapped PCI express config space
+OperationRegion (PCIC, SystemMemory, CONFIG_ECAM_MMCONF_BASE_ADDRESS + (CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 15), 0x1000)
+
+Field (PCIC, ByteAcc, NoLock, Preserve) {
+ PVID, 16,
+ PDID, 16,
+
+ Offset (0x248),
+ , 7,
+ L23E, 1, /* L23_Rdy Entry Request */
+ L23R, 1, /* L23_Rdy to Detect Transition */
+
+ Offset (0xC20),
+ , 4,
+ P0AP, 2, /* Additional power savings */
+
+ Offset (0xC38),
+ , 3,
+ P0RM, 1, /* Robust squelch mechanism */
+}
+
+// Enter L23
+Method (DL23, 0, Serialized) {
+ Printf(" GPU PORT DL23 START")
+
+ L23E = 1
+ Sleep (16)
+ Local0 = 0
+ While (L23E) {
+ If ((Local0 > 4)) {
+ Break
+ }
+
+ Sleep (16)
+ Local0++
+ }
+
+ P0RM = 1
+ P0AP = 3
+
+ Printf(" GPU PORT DL23 FINISH")
+}
+
+// Exit L23
+Method (L23D, 0, Serialized) {
+ Printf(" GPU PORT L23D START")
+
+ L23R = 1
+ Sleep (16)
+ Local0 = 0
+ While (L23R) {
+ If ((Local0 > 4)) {
+ Break
+ }
+
+ Sleep (16)
+ Local0++
+ }
+
+ P0RM = 0
+ P0AP = 0
+
+ Printf(" GPU PORT L23D FINISH")
+}
+
+// Main power resource
+PowerResource (PWRR, 0, 0) {
+ Name (_STA, 1)
+
+ Method (_ON, 0, Serialized) {
+ Printf("GPU PORT PWRR._ON")
+
+ ^^DEV0._ON()
+
+ _STA = 1
+ }
+
+ Method (_OFF, 0, Serialized) {
+ Printf("GPU PORT PWRR._OFF")
+
+ ^^DEV0._OFF()
+
+ _STA = 0
+ }
+}
+
+// Power resources for entering D0
+Name (_PR0, Package () { PWRR })
+
+// Power resources for entering D3
+Name (_PR3, Package () { PWRR })
+
+#include "common/gpu.asl"

src/drivers/gfx/nvidia/acpi/common/dsm.asl

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+#include "nvjt.asl"
+
+Method (_DSM, 4, Serialized) {
+ Printf("GPU _DSM")
+ If (Arg0 == ToUUID (JT_DSM_GUID)) {
+ If (ToInteger(Arg1) >= JT_REVISION_ID_MIN) {
+ Return (NVJT(Arg2, Arg3))
+ } Else {
+ Printf(" Unsupported JT revision: %o", SFST(Arg1))
+ Return (NV_ERROR_UNSUPPORTED)
+ }
+ } ElseIf (Arg0 == ToUUID (GPS_DSM_GUID)) {
+ If (ToInteger(Arg1) == GPS_REVISION_ID) {
+ Return (GPS(Arg2, Arg3))
+ } Else {
+ Printf(" Unsupported GPS revision: %o", SFST(Arg1))
+ Return (NV_ERROR_UNSUPPORTED)
+ }
+ } Else {
+ Printf(" Unsupported GUID: %o", IDST(Arg0))
+ Return (NV_ERROR_UNSPECIFIED)
+ }
+}

src/drivers/gfx/nvidia/acpi/common/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+ Printf(" GPU GPS")
+ Switch(ToInteger(Arg0)) {
+ Case(GPS_FUNC_SUPPORT) {
+ Printf(" Supported Functions")
+ Return(ITOB(
+ (1 << GPS_FUNC_SUPPORT) |
+ (1 << GPS_FUNC_PSHARESTATUS) |
+ (1 << GPS_FUNC_PSHAREPARAMS)
+ ))
+ }
+ Case(GPS_FUNC_PSHARESTATUS) {
+ Printf(" Power Share Status")
+ Return(ITOB(0))
+ }
+ Case(GPS_FUNC_PSHAREPARAMS) {
+ Printf(" Power Share Parameters")
+
+ CreateField(Arg1, 0, 4, QTYP) // Query type
+
+ Name(GPSP, Buffer(36) { 0x00 })
+ CreateDWordField(GPSP, 0, RSTS) // Response status
+ CreateDWordField(GPSP, 4, VERS) // Version
+
+ // Set query type of response
+ RSTS = QTYP
+ // Set version of response
+ VERS = 0x00010000
+
+ Switch(ToInteger(QTYP)) {
+ Case(0) {
+ Printf(" Request Current Information")
+ // No required information
+ Return(GPSP)
+ }
+ Case(1) {
+ Printf(" Request Supported Fields")
+ // Support GPU temperature field
+ RSTS |= (1 << 8)
+ Return(GPSP)
+ }
+ Case(2) {
+ Printf(" Request Current Limits")
+ // No required limits
+ Return(GPSP)
+ }
+ Default {
+ Printf(" Unknown Query: %o", SFST(QTYP))
+ Return(NV_ERROR_UNSUPPORTED)
+ }
+ }
+ }
+ Default {
+ Printf(" Unsupported function: %o", SFST(Arg0))
+ Return(NV_ERROR_UNSUPPORTED)
+ }
+ }
+}

src/drivers/gfx/nvidia/acpi/common/gpu.asl

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+ Name(_ADR, 0x00000000)
+
+ #include "utility.asl"
+ #include "dsm.asl"
+ #include "power.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+ Device(NPCF) {
+ #include "utility.asl"
+ #include "nvpcf.asl"
+ }
+}
+#endif