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soc/intel/alderlake: Add RPL-S GPIO ACPI ID #194

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merged 2 commits into from
Aug 23, 2023
Merged

soc/intel/alderlake: Add RPL-S GPIO ACPI ID #194

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soc/intel/alderlake: Add RPL-S GPIO ACPI ID
jackpot51 Aug 23, 2023
982ad80
soc/intel/alderlake: Hack to preserve SBREG
jackpot51 Aug 23, 2023
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5 changes: 5 additions & 0 deletions src/soc/intel/alderlake/include/soc/gpio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,13 @@

#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#include <soc/gpio_defs_pch_s.h>
#if CONFIG(SOC_INTEL_RAPTORLAKE)
#define CROS_GPIO_NAME "INTC1085"
#define CROS_GPIO_DEVICE_NAME "INTC1085:00"
#else
#define CROS_GPIO_NAME "INTC1056"
#define CROS_GPIO_DEVICE_NAME "INTC1056:00"
#endif
#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
#include <soc/gpio_defs.h>
#define CROS_GPIO_NAME "INTC1057"
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6 changes: 6 additions & 0 deletions src/soc/intel/alderlake/include/soc/iomap.h
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Expand Up @@ -20,8 +20,14 @@
#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
#endif

/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#define PCH_PRESERVED_BASE_ADDRESS 0xe0000000
#define PCH_PRESERVED_BASE_SIZE 0x1e800000
#else
#define PCH_PRESERVED_BASE_ADDRESS 0xfc800000
#define PCH_PRESERVED_BASE_SIZE 0x02000000
#endif

#define UART_BASE_SIZE 0x1000

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