Zicond extension

include/AllRevInstTables.h

@@ -32,6 +32,7 @@
 #include "insns/Zalrsc.h"
 #include "insns/Zfa.h"
 #include "insns/Zicbom.h"
+#include "insns/Zicond.h"
 #include "insns/Zicsr.h"
 #include "insns/Zifencei.h"
 

include/RevFeature.h

@@ -36,15 +36,16 @@ enum RevFeatureType : uint32_t {
   RV_H        = 1 << 10,  ///< RevFeatureType: H-extension
   RV_ZICBOM   = 1 << 11,  ///< RevFeatureType: Zicbom-extension
   RV_ZICNTR   = 1 << 12,  ///< RevFeatureType: Zicntr-extension
-  RV_ZICSR    = 1 << 13,  ///< RevFEatureType: Zicsr-extension
-  RV_ZIFENCEI = 1 << 14,  ///< RevFeatureType: Zifencei-extension
-  RV_ZMMUL    = 1 << 15,  ///< RevFeatureType: Zmmul-extension
-  RV_ZAAMO    = 1 << 16,  ///< RevFeatureType: Zaamo-extension
-  RV_ZALRSC   = 1 << 17,  ///< RevFeatureType: Zalrsc-extension
-  RV_ZFA      = 1 << 18,  ///< RevFeatureType: Zfa-extension
-  RV_ZFH      = 1 << 19,  ///< RevFeatureType: H-extension
-  RV_ZFHMIN   = 1 << 20,  ///< RevFeatureRtpe: Zfhmin extension
-  RV_ZTSO     = 1 << 21,  ///< RevFeatureType: Ztso-extension
+  RV_ZICOND   = 1 << 13,  ///< RevFeatureType: Zicond-extension
+  RV_ZICSR    = 1 << 14,  ///< RevFEatureType: Zicsr-extension
+  RV_ZIFENCEI = 1 << 15,  ///< RevFeatureType: Zifencei-extension
+  RV_ZMMUL    = 1 << 16,  ///< RevFeatureType: Zmmul-extension
+  RV_ZAAMO    = 1 << 17,  ///< RevFeatureType: Zaamo-extension
+  RV_ZALRSC   = 1 << 18,  ///< RevFeatureType: Zalrsc-extension
+  RV_ZFA      = 1 << 19,  ///< RevFeatureType: Zfa-extension
+  RV_ZFH      = 1 << 20,  ///< RevFeatureType: H-extension
+  RV_ZFHMIN   = 1 << 21,  ///< RevFeatureRtpe: Zfhmin extension
+  RV_ZTSO     = 1 << 22,  ///< RevFeatureType: Ztso-extension
 };
 
 class RevFeature {

include/insns/Zicond.h

@@ -0,0 +1,68 @@
+//
+// _Zicond_h_
+//
+// Copyright (C) 2017-2024 Tactical Computing Laboratories, LLC
+// All Rights Reserved
+// contact@tactcomplabs.com
+//
+// See LICENSE in the top level directory for licensing details
+//
+
+#ifndef _SST_REVCPU_ZICOND_H_
+#define _SST_REVCPU_ZICOND_H_
+
+#include "../RevExt.h"
+#include "../RevInstHelpers.h"
+
+namespace SST::RevCPU {
+
+class Zicond : public RevExt {
+
+  template<template<typename> class CMP>
+  static bool czero( RevFeature* F, RevRegFile* R, RevMem* M, const RevInst& Inst ) {
+    if( R->IsRV32 ) {
+      R->SetX( Inst.rd, CMP()( R->GetX<uint32_t>( Inst.rs2 ), 0 ) ? 0 : R->GetX<uint32_t>( Inst.rs1 ) );
+    } else {
+      R->SetX( Inst.rd, CMP()( R->GetX<uint64_t>( Inst.rs2 ), 0 ) ? 0 : R->GetX<uint64_t>( Inst.rs1 ) );
+    }
+    R->AdvancePC( Inst );
+    return true;
+  }
+
+  static constexpr auto& czero_eqz = czero<std::equal_to>;
+  static constexpr auto& czero_nez = czero<std::not_equal_to>;
+
+  // ----------------------------------------------------------------------
+  //
+  // RISC-V Zicond Instructions
+  //
+  // ----------------------------------------------------------------------
+  struct RevZicondInstDefaults : RevInstDefaults {
+    RevZicondInstDefaults() {
+      SetOpcode( 0b0110011 );
+      SetFunct2or7( 0b0000111 );
+    }
+  };
+
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+  // Single-Precision Instructions
+  /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+  // clang-format off
+  std::vector<RevInstEntry> ZicondTable = {
+    RevZicondInstDefaults().SetMnemonic( "czero.eqz %rd, %rs1, %rs2" ).SetFunct3( 0b101 ).SetImplFunc( czero_eqz ),
+    RevZicondInstDefaults().SetMnemonic( "czero.nez %rd, %rs1, %rs2" ).SetFunct3( 0b111 ).SetImplFunc( czero_nez ),
+  };
+
+  // clang-format on
+
+public:
+  /// Zicond: standard constructor
+  Zicond( RevFeature* Feature, RevMem* RevMem, SST::Output* Output ) : RevExt( "Zicond", Feature, RevMem, Output ) {
+    SetTable( std::move( ZicondTable ) );
+  }
+};  // end class Zicond
+
+}  // namespace SST::RevCPU
+
+#endif

src/RevCore.cc

@@ -199,6 +199,11 @@ bool RevCore::SeedInstTable() try {
     EnableExt( new Zicbom( feature, mem, output ) );
   }
 
+  // Zicond Extension
+  if( feature->IsModeEnabled( RV_ZICOND ) ) {
+    EnableExt( new Zicond( feature, mem, output ) );
+  }
+
   // Zicsr Extension
   if( feature->IsModeEnabled( RV_ZICSR ) ) {
     EnableExt( new Zicsr( feature, mem, output ) );

src/RevFeature.cc

@@ -72,6 +72,7 @@ bool RevFeature::ParseMachineModel() {
     { "H",          1, 0, -1, 0, RV_H                                   }, // Unsupported
     { "Zicbom",     1, 0,  1, 1, RV_ZICBOM                              },
     { "Zicntr",     2, 0,  2, 2, RV_ZICNTR | RV_ZICSR                   },
+    { "Zicond",     1, 0,  1, 1, RV_ZICOND                              },
     { "Zicsr",      2, 0,  2, 2, RV_ZICSR                               },
     { "Zifencei",   2, 0,  2, 2, RV_ZIFENCEI                            },
     { "Zmmul",      1, 0,  1, 1, RV_ZMMUL                               },