Tweak format of asm

taiki-e · Dec 16, 2023 · 29da276 · 29da276
1 parent 49a50f2
commit 29da276
Show file tree

Hide file tree

Showing 3 changed files with 34 additions and 10 deletions.
diff --git a/src/imp/atomic128/detect/aarch64_aa64reg.rs b/src/imp/atomic128/detect/aarch64_aa64reg.rs
@@ -109,7 +109,7 @@ mod imp {
             asm!(
                 "mrs {0}, ID_AA64ISAR0_EL1",
                 out(reg) aa64isar0,
-                options(pure, nomem, nostack, preserves_flags)
+                options(pure, nomem, nostack, preserves_flags),
             );
             #[cfg(test)]
             let aa64isar1: u64;
@@ -118,14 +118,14 @@ mod imp {
                 asm!(
                     "mrs {0}, ID_AA64ISAR1_EL1",
                     out(reg) aa64isar1,
-                    options(pure, nomem, nostack, preserves_flags)
+                    options(pure, nomem, nostack, preserves_flags),
                 );
             }
             let aa64mmfr2: u64;
             asm!(
                 "mrs {0}, ID_AA64MMFR2_EL1",
                 out(reg) aa64mmfr2,
-                options(pure, nomem, nostack, preserves_flags)
+                options(pure, nomem, nostack, preserves_flags),
             );
             AA64Reg {
                 aa64isar0,

diff --git a/src/imp/atomic128/detect/auxv.rs b/src/imp/atomic128/detect/auxv.rs
@@ -283,7 +283,7 @@ mod tests {
                         // arg4 and arg5 must be zero.
                         in("x3") 0_u64,
                         in("x4") 0_u64,
-                        options(nostack, preserves_flags)
+                        options(nostack, preserves_flags),
                     );
                 }
                 #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]
@@ -315,7 +315,7 @@ mod tests {
                         out("r11") _,
                         out("r12") _,
                         out("cr0") _,
-                        options(nostack, preserves_flags)
+                        options(nostack, preserves_flags),
                     );
                 }
                 #[allow(clippy::cast_possible_truncation, clippy::cast_sign_loss)]
@@ -586,7 +586,7 @@ mod tests {
                         out("r11") _,
                         out("r12") _,
                         out("cr0") _,
-                        options(nostack, preserves_flags)
+                        options(nostack, preserves_flags),
                     );
                     if r as c_int == -1 {
                         Err(n as c_int)

diff --git a/src/imp/riscv.rs b/src/imp/riscv.rs
@@ -72,9 +72,21 @@ fn sllw(val: u32, shift: u32) -> u32 {
     unsafe {
         let out;
         #[cfg(target_arch = "riscv32")]
-        asm!("sll {out}, {val}, {shift}", out = lateout(reg) out, val = in(reg) val, shift = in(reg) shift, options(pure, nomem, nostack, preserves_flags));
+        asm!(
+            "sll {out}, {val}, {shift}",
+            out = lateout(reg) out,
+            val = in(reg) val,
+            shift = in(reg) shift,
+            options(pure, nomem, nostack, preserves_flags),
+        );
         #[cfg(target_arch = "riscv64")]
-        asm!("sllw {out}, {val}, {shift}", out = lateout(reg) out, val = in(reg) val, shift = in(reg) shift, options(pure, nomem, nostack, preserves_flags));
+        asm!(
+            "sllw {out}, {val}, {shift}",
+            out = lateout(reg) out,
+            val = in(reg) val,
+            shift = in(reg) shift,
+            options(pure, nomem, nostack, preserves_flags),
+        );
         out
     }
 }
@@ -86,9 +98,21 @@ fn srlw(val: u32, shift: u32) -> u32 {
     unsafe {
         let out;
         #[cfg(target_arch = "riscv32")]
-        asm!("srl {out}, {val}, {shift}", out = lateout(reg) out, val = in(reg) val, shift = in(reg) shift, options(pure, nomem, nostack, preserves_flags));
+        asm!(
+            "srl {out}, {val}, {shift}",
+            out = lateout(reg) out,
+            val = in(reg) val,
+            shift = in(reg) shift,
+            options(pure, nomem, nostack, preserves_flags),
+        );
         #[cfg(target_arch = "riscv64")]
-        asm!("srlw {out}, {val}, {shift}", out = lateout(reg) out, val = in(reg) val, shift = in(reg) shift, options(pure, nomem, nostack, preserves_flags));
+        asm!(
+            "srlw {out}, {val}, {shift}",
+            out = lateout(reg) out,
+            val = in(reg) val,
+            shift = in(reg) shift,
+            options(pure, nomem, nostack, preserves_flags),
+        );
         out
     }
 }