docs: Document about {64,128}-bit atomics in more architectures

.github/.cspell/project-dictionary.txt

@@ -14,6 +14,7 @@ bitops
 BOOKE
 callthru
 casp
+casx
 cbnz
 ccmp
 cdsg
@@ -41,7 +42,6 @@ cxchg
 cxchgweak
 dlfcn
 dlsym
-DWCAS
 ecall
 EINVAL
 elems
@@ -87,6 +87,8 @@ libstd
 libtcl
 libtest
 linkall
+lldp
+llwp
 lmul
 locgr
 locgre
@@ -97,6 +99,7 @@ machdep
 MAXNAME
 maxu
 mcpu
+memd
 mfcr
 mfence
 mgba
@@ -135,6 +138,8 @@ rsend
 rsil
 RTLD
 sbcs
+scdp
+scwp
 selgr
 seqlock
 setb

src/imp/atomic128/README.md

@@ -13,6 +13,7 @@ Here is the table of targets that support 128-bit atomics and the instructions u
 | riscv64 | amocas.q | amocas.q | amocas.q | amocas.q | Experimental because LLVM marking the corresponding target feature as experimental. Requires `experimental-zacas` target feature. Both compile-time and run-time detection are supported (run-time detection is currently disabled by default). <br> Requires rustc 1.59+ |
 | powerpc64 | lq | stq | lqarx/stqcx. | lqarx/stqcx. | Requires `quadword-atomics` target feature (enabled by default on powerpc64le). Both compile-time and run-time detection are supported. <br> Requires nightly |
 | s390x | lpq | stpq | cdsg | cdsg | Requires rustc 1.84+ |
+| mips64r6 | lldp | lldp/scdp | lldp/scdp | lldp/scdp | Unimplemented (unsupported in LLVM). Requires Release 6 Paired LL/SC family of instructions |
 
 On compiler versions or platforms where these are not supported, the fallback implementation is used.
 

src/imp/atomic128/aarch64.rs

@@ -3,13 +3,13 @@
 /*
 128-bit atomic implementation on AArch64.
 
-There are a few ways to implement 128-bit atomic operations in AArch64.
+This architecture provides the following 128-bit atomic instructions:
 
-- LDXP/STXP loop (DW LL/SC)
-- CASP (DWCAS) added as Armv8.1 FEAT_LSE (optional from Armv8.0, mandatory from Armv8.1)
-- LDP/STP (DW load/store) if Armv8.4 FEAT_LSE2 (optional from Armv8.2, mandatory from Armv8.4) is available
-- LDIAPP/STILP (DW acquire-load/release-store) added as Armv8.9 FEAT_LRCPC3 (optional from Armv8.2) (if FEAT_LSE2 is also available)
-- LDCLRP/LDSETP/SWPP (DW RMW) added as Armv9.4 FEAT_LSE128 (optional from Armv9.3)
+- LDXP/STXP: LL/SC (Armv8.0 baseline)
+- CASP: CAS (added as Armv8.1 FEAT_LSE (optional from Armv8.0, mandatory from Armv8.1))
+- LDP/STP: load/store (if Armv8.4 FEAT_LSE2 (optional from Armv8.2, mandatory from Armv8.4) is available)
+- LDIAPP/STILP: acquire-load/release-store (added as Armv8.9 FEAT_LRCPC3 (optional from Armv8.2) (if FEAT_LSE2 is also available))
+- LDCLRP/LDSETP/SWPP: fetch-and-{clear,or},swap (added as Armv9.4 FEAT_LSE128 (optional from Armv9.3))
 
 This module supports all of these instructions and attempts to select the best
 one based on compile-time and run-time information about available CPU features

src/imp/atomic128/x86_64.rs

@@ -1,7 +1,12 @@
 // SPDX-License-Identifier: Apache-2.0 OR MIT
 
 /*
-128-bit atomic implementation on x86_64 using CMPXCHG16B (DWCAS).
+128-bit atomic implementation on x86_64.
+
+This architecture provides the following 128-bit atomic instructions:
+
+- CMPXCHG16B: CAS (CMPXCHG16B)
+- VMOVDQA: load/store (Intel, AMD, or Zhaoxin CPU with AVX)
 
 Note: On Miri and ThreadSanitizer which do not support inline assembly, we don't use
 this module and use intrinsics.rs instead.

src/imp/atomic64/README.md

@@ -11,6 +11,10 @@ Here is the table of targets that support 64-bit atomics and the instructions us
 | x86 | cmpxchg8b or fild or movlps or movq | cmpxchg8b or fistp or movlps | cmpxchg8b | cmpxchg8b | provided by `core::sync::atomic` |
 | arm | ldrexd | ldrexd/strexd | ldrexd/strexd | ldrexd/strexd | provided by `core::sync::atomic` for Armv6+, otherwise provided by us for Linux/Android using kuser_cmpxchg64 (see [arm_linux.rs](arm_linux.rs) for more) |
 | riscv32 | amocas.d | amocas.d | amocas.d | amocas.d | Experimental because LLVM marking the corresponding target feature as experimental. Requires `experimental-zacas` target feature. Both compile-time and run-time detection are supported (run-time detection is currently disabled by default). <br> Requires rustc 1.59+ |
+| hexagon | memd | memd | memd_locked | memd_locked | Unimplemented |
+| sparc | ldx | stx | casx | casx | Unimplemented (unsupported in LLVM). Requires `v8plus` and `v9` target feature (Linux is v8plus+v9 by default) |
+| m68k | cas2 | cas2 | cas2 | cas2 | Unimplemented (unsupported in LLVM). Requires M68020 or later (Linux is M68020 by default) |
+| mips32r6 | llwp | llwp/scwp | llwp/scwp | llwp/scwp | Unimplemented (unsupported in LLVM). Requires Release 6 Paired LL/SC family of instructions |
 
 If `core::sync::atomic` provides 64-bit atomics, we use them.
 On compiler versions or platforms where these are not supported, the fallback implementation is used.