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Support Xtensa (OpenOCD Semihosting) #9
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Thanks for the PR. Just created probe-rs/probe-rs#2301, once that this issue is solved we will have a way to test this PR. If you have any suggestion on how to test this Pr alone, just let me know! |
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I was able to run some tests in an ESP32-S3 (Xtensa)!
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Thanks for the PR @taiki-e, it's very much appreciated!
I can't rule out other Xtensa players wanting to use the simcall method, so I think the safest method would be to put this behind a feature, which leaves the option of adding a simcall implementation down the line. It may also be beneficial for Espressif, as we do have QEMU support for some of our chips, and QEMU uses the simcall method of semihosting. |
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Moved this implementation behind the Document of the feature is:
And here is the error message when using this crate on Xtensa without enabling the
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Published in 0.1.7. |
This supports ARM-semihosting-compatible OpenOCD Semihosting that using
break
instruction, under theopenocd-semihosting
feature.I'm currently thinking there are two blockers to merge this:
cargo +esp build --target xtensa-esp32-none-elf -Z build-std=core,alloc --features alloc,stdio,fs,args,time
, but as said in Support for Xtensa architecture #8 (comment), I don't have the environment to test this. We need to have someone check that this works before we merge it.simcall
-based semihosting, I think this PR is fine as is, but if not, it would be safer to add a feature flag and enable the implementation only when it is enabled, rather than unconditionally enabling this implementation.openocd-semihosting
feature. Support Xtensa (OpenOCD Semihosting) #9 (comment)cc @SergioGasquez
Closes #8