+ bus lib, documentation and tb_replicate

casper_bus/run.py

@@ -27,6 +27,10 @@
 casper_accumulators_lib = vu.add_library("casper_accumulators_lib")
 casper_accumulators_lib.add_source_files(join(script_dir, "../casper_accumulators/simple_accumulator.vhd"))
 
+# Create library 'casper_flow_control_lib'
+casper_flow_control_lib = vu.add_library("casper_flow_control_lib")
+casper_flow_control_lib.add_source_files(join(script_dir, "../casper_flow_control/bus_create.vhd"))
+
 
 # CASPER BUS Library
 casper_bus_lib = vu.add_library("casper_bus_lib")
@@ -45,6 +49,18 @@
                 }
             )
 
+TB_REPLICATE = casper_bus_lib.test_bench("tb_tb_vu_replicate")
+for delay in [0,1,2]:
+    for replication_factor in [2, 3]:
+        TB_REPLICATE.add_config(
+            name = f"Replicate (x{replication_factor}) with delay {delay}",
+            generics={
+                "g_replication_factor": replication_factor,
+                "g_latency": delay,
+                "g_replicated_value": 6
+            }
+        )
+
 TB_BUS_ACC = casper_bus_lib.test_bench("tb_tb_vu_bus_accumulator")
 TB_BUS_ACC.add_config(
     name = f"Bus Accumulator",

casper_bus/tb_bus_replicate.vhd

@@ -0,0 +1,86 @@
+-- A VHDL testbench for CASPER bus_replicate block.
+-- @author: Ross Donnachie
+-- @company: Mydon Solutions
+
+LIBRARY IEEE, common_pkg_lib;
+USE IEEE.std_logic_1164.all;
+USE common_pkg_lib.common_pkg.ALL;
+
+ENTITY tb_bus_replicate is
+  generic (
+    g_replication_factor : NATURAL := 2;
+    g_latency : NATURAL := 0;
+    g_replicated_value : NATURAL := 6
+  );
+  port (
+    o_clk   : out std_logic;
+    o_tb_end : out std_logic;
+    o_test_msg : out STRING(1 to 80);
+    o_test_pass : out BOOLEAN  
+  );
+end ENTITY;
+
+ARCHITECTURE rtl of tb_bus_replicate is
+  CONSTANT clk_period : TIME    := 10 ns;
+
+  SIGNAL clk : std_logic := '1';
+  SIGNAL ce : std_logic := '1';
+  SIGNAL tb_end  : STD_LOGIC := '0';
+
+  CONSTANT bit_width : NATURAL := ceil_log2(g_replicated_value);
+
+  SIGNAL s_in : std_logic_vector(bit_width-1 downto 0) := (others => '0');
+  SIGNAL s_out : std_logic_vector((bit_width*g_replication_factor)-1 downto 0) := (others => '0');
+begin
+
+  clk  <= NOT clk OR tb_end AFTER clk_period / 2;
+
+  o_clk <= clk;
+  o_tb_end <= tb_end;
+
+  u_bus_replicate : entity work.bus_replicate
+    generic map (
+      g_replication_factor => g_replication_factor,
+      g_latency => g_latency
+    )
+    port map (
+      clk => clk,
+      ce => ce,
+
+      i_data => s_in,
+      o_data => s_out
+    );
+
+  p_stim: process
+    variable v_din_index, v_dout_index: integer;
+    VARIABLE v_test_pass : BOOLEAN := TRUE;
+    VARIABLE v_test_msg  : STRING(1 to o_test_msg'length) := (OTHERS => '.');
+  begin
+    ce <= '0';
+    s_in <= std_logic_vector(to_unsigned(g_replicated_value, bit_width));
+
+    wait until rising_edge(clk);
+    wait for 3*clk_period;
+    ce <= '1';
+    wait for g_latency*clk_period;
+
+    for r in 0 to g_replication_factor loop
+      if g_replicated_value /= unsigned(s_out(
+          ((r+1)*bit_width)-1 downto (r*bit_width)
+      )) then
+        v_test_msg := pad("Replication #"& integer'image(r) &" failed. Expected: " & integer'image(g_replicated_value) & " but got: " & integer'image(to_integer(unsigned(s_dout(
+          ((r+1)*bit_width)-1 downto (r*bit_width)
+        )))), o_test_msg'length, '.');
+        v_test_pass := FALSE;
+        REPORT v_test_msg severity failure;
+      end if;
+
+      o_test_msg <= v_test_msg;
+      o_test_pass <= v_test_pass;
+    end loop;
+
+    tb_end <= '1';
+    wait;
+  end process;
+
+end ARCHITECTURE;

casper_bus/tb_tb_vu_bus_replicate.vhd

@@ -0,0 +1,62 @@
+LIBRARY IEEE, common_pkg_lib, vunit_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_pkg_lib.common_pkg.ALL;
+context vunit_lib.vunit_context;
+
+ENTITY tb_tb_vu_bus_replicate IS
+	GENERIC(
+		g_replication_factor : NATURAL := 2;
+		g_latency 			 : NATURAL := 0;
+		g_replicated_value 	 : NATURAL := 6;
+		runner_cfg      : string
+	);
+END tb_tb_vu_bus_replicate;
+
+ARCHITECTURE tb OF tb_tb_vu_bus_replicate IS
+
+	SIGNAL rst      	: STD_LOGIC;
+	SIGNAL clk      	: STD_LOGIC;
+	SIGNAL tb_end   	: STD_LOGIC;
+	SIGNAL test_msg   : STRING(1 to 80);
+	SIGNAL test_pass	: BOOLEAN;
+
+	SIGNAL s_test_count : natural := 0;
+BEGIN
+
+	tb_ut : ENTITY work.tb_bus_replicate
+		GENERIC MAP(
+			g_replication_factor => g_replication_factor,
+			g_latency			 => g_latency,
+			g_replicated_value	 => g_replicated_value
+		)
+		PORT MAP(
+			o_clk => clk,
+			o_tb_end => tb_end,
+			o_test_msg => test_msg,
+			o_test_pass => test_pass
+		);
+
+	p_vunit : PROCESS
+	BEGIN
+		test_runner_setup(runner, runner_cfg);
+		wait until tb_end = '1';
+		test_runner_cleanup(runner);
+		wait;
+	END PROCESS;
+
+
+	p_verify : PROCESS(rst, clk)
+	BEGIN
+		IF rst = '0' THEN
+			IF rising_edge(clk) THEN
+				check(test_pass, "Test Failed: " & test_msg);
+				IF tb_end THEN
+					report "Tests completed: " & integer'image(s_test_count+1);
+				END IF;
+				s_test_count <= 1;
+			END IF;
+		END IF;
+
+	END PROCESS;
+END tb;

docs/source/bus.rst

@@ -0,0 +1,130 @@
+####################
+Bus Library
+####################
+.. _bus:
+
+*******
+Purpose
+*******
+.. _bus_purpose:
+
+The bus library contains all casper_bus HDL modules wrapped for Simulink.
+These blocks manipulate standard logic-vectors in conventional ways. "Sub-vector" is a term
+used to refer to a slice or sub-section of the overall logic-vector.
+
+===============
+Bus Accumulator
+===============
+Applies individual accumulators (:ref:`Accumulator Library<accumulator>`) to sub-vectors.
+
+-----
+Ports
+-----
++-------------+-----------------+------------+-------------------------------------------------+
+| Signal      | Type            | Size       | Description                                     |
++=============+=================+============+=================================================+
+| din         | std_logic_vector| any        | The input vector, constituted by the sub-vectors|
+|             |                 |            | that are accumulated.                           |
++-------------+-----------------+------------+-------------------------------------------------+
+| dout        | std_logic_vector| any        | The output vector of accumulations, each        |
+|             |                 |            | expanded.                                       |  
++-------------+-----------------+------------+-------------------------------------------------+
+
+----------
+Parameters
+----------
++---------------------+------------------+----------+------------------------------------------------------------+
+| Generic             | Type             | Value    | Description                                                |
++=====================+==================+==========+============================================================+
+| Data Type           | "UNSIGNED" or    | "SIGNED" | The switch to treat the sub-vectors as signed or unsigned. |
+|                     | "SIGNED"         |          |                                                            |
++---------------------+------------------+----------+------------------------------------------------------------+
+| Constituent Widths  | Comma-delimited  | 4,1,2,1  | The bit-width of each sub-vector.                          |
+|                     | Integers         |          |                                                            |
++---------------------+------------------+----------+------------------------------------------------------------+
+| Constituent         | Comma-delimited  | 9,6,7,6  | The bit-width of each accumulated output sub-vector.       |
+| Expansion Widths    | Integers         |          |                                                            |
++---------------------+------------------+----------+------------------------------------------------------------+
+
+==================
+Bus Fill SLV Array
+==================
+Duplicates an input standard logic-vector to each index of an output array. This is not exposed to simulink due to
+the use of the custom `t_slv_arr` type in the interface.
+
+-----
+Ports
+-----
++-------------+-----------------+------------+-------------------------------------------------+
+| Signal      | Type            | Size       | Description                                     |
++=============+=================+============+=================================================+
+| i_data      | std_logic_vector| any        | The input vector.                               |
++-------------+-----------------+------------+-------------------------------------------------+
+| o_data      | t_slv_arr       | (any, any) | The output vectors, duplications of the input.  |  
++-------------+-----------------+------------+-------------------------------------------------+
+
+----------
+Parameters
+----------
++---------------------+------------------+----------+------------------------------------------------------------+
+| Generic             | Type             | Value    | Description                                                |
++=====================+==================+==========+============================================================+
+| Latency             | Natural          |          | The latency of the duplication.                            |
++---------------------+------------------+----------+------------------------------------------------------------+
+
+===========
+Bus Mux
+===========
+Multiplexes an input standard logic-array, outputing one selected (by index) standard logic vector.
+
+-----
+Ports
+-----
++-------------+-----------------+------------+-------------------------------------------------+
+| Signal      | Type            | Size       | Description                                     |
++=============+=================+============+=================================================+
+| i_sel       | std_logic_vector| any        | The index selection.                            |
++-------------+-----------------+------------+-------------------------------------------------+
+| i_data      | t_slv_arr       | (any, any) | The input vectors.                              |
++-------------+-----------------+------------+-------------------------------------------------+
+| o_data      | std_logic_vector| any        | The selection, output vector.                   |  
++-------------+-----------------+------------+-------------------------------------------------+
+
+----------
+Parameters
+----------
++---------------------+------------------+----------+------------------------------------------------------------+
+| Generic             | Type             | Value    | Description                                                |
++=====================+==================+==========+============================================================+
+| Delay               | Natural          | 1        | The latency of the multiplexion.                           |
++---------------------+------------------+----------+------------------------------------------------------------+
+
+
+==================
+Bus Replicate
+==================
+Concatenates duplications of an input standard logic-vector to an output logic-vector. This essentially flattens
+the output of the Fill SLV Array component.
+
+-----
+Ports
+-----
++-------------+-----------------+------------+-------------------------------------------------+
+| Signal      | Type            | Size       | Description                                     |
++=============+=================+============+=================================================+
+| i_data      | std_logic_vector| any        | The input vector.                               |
++-------------+-----------------+------------+-------------------------------------------------+
+| o_data      | std_logic_vector| any        | The output vector, concatenated duplications of |
+|             |                 |            | the input.                                      |
++-------------+-----------------+------------+-------------------------------------------------+
+
+----------
+Parameters
+----------
++---------------------+------------------+----------+------------------------------------------------------------+
+| Generic             | Type             | Value    | Description                                                |
++=====================+==================+==========+============================================================+
+| Replication Factor  | Natural          |          | The number of duplications.                                |
++---------------------+------------------+----------+------------------------------------------------------------+
+| Latency             | Natural          |          | The latency of the duplication.                            |
++---------------------+------------------+----------+------------------------------------------------------------+

docs/source/index.rst

@@ -10,6 +10,7 @@ IP Cores:
    :maxdepth: 5
 
    accumulators
+   bus
    delay
    flow_control
    multiplier