atomic: Fix RISC-V build with GCC < 14

Prior to GCC 14.1, the __builtin_riscv_pause() can cause an error if the
appropriate extension is not enabled in -march:

    /tmp/ccR1L1lA.s: Assembler messages:
    /tmp/ccR1L1lA.s:670: Error: unrecognized opcode `pause', extension `zihintpause' required

Link: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626748.html
Link: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c2d04dd659c499d8df19f68d0602ad4c7d7065c2
Link: https://buildd.debian.org/status/fetch.php?pkg=bfs&arch=riscv64&ver=3.3.1-1&stamp=1717488400&raw=0

build/has/builtin-riscv-pause.c

@@ -0,0 +1,7 @@
+// Copyright © Tavian Barnes <tavianator@tavianator.com>
+// SPDX-License-Identifier: 0BSD
+
+int main(void) {
+	__builtin_riscv_pause();
+	return 0;
+}

build/header.mk

@@ -16,6 +16,7 @@ HEADERS := \
     gen/has/acl-is-trivial-np.h \
     gen/has/acl-trivial.h \
     gen/has/aligned-alloc.h \
+    gen/has/builtin-riscv-pause.h \
     gen/has/confstr.h \
     gen/has/extattr-get-file.h \
     gen/has/extattr-get-link.h \

src/atomic.h

@@ -109,7 +109,7 @@
 #  define spin_loop() __builtin_ia32_pause()
 #elif __has_builtin(__builtin_arm_yield)
 #  define spin_loop() __builtin_arm_yield()
-#elif __has_builtin(__builtin_riscv_pause)
+#elif BFS_HAS_BUILTIN_RISCV_PAUSE
 #  define spin_loop() __builtin_riscv_pause()
 #else
 #  define spin_loop() ((void)0)