Add support for pre_cmd parameter to match cocotb v1.9

README.md

@@ -68,6 +68,7 @@ cocotb-clean -r
 * `sim_args`: Any arguments or flags to pass to the execution of the compiled simulation.
 * `extra_args`: Passed to both the compile and execute phases of simulators.
 * `plus_args`: plusargs arguments passed to simulator.
+* `pre_cmd`: Commands to run before simulation begins (currently only available for the Questa simulator).
 * `force_compile`: Force compilation even if sources did not change. (default: `False`)
 * `compile_only`: Only compile sources. Do not run simulation. (default: `False`)
 * `testcase`: The name of the test function(s) to run (see [TESTCASE](https://docs.cocotb.org/en/stable/building.html?#envvar-TESTCASE) ).

cocotb_test/simulator.py

@@ -54,6 +54,7 @@ def __init__(
  sim_args=None,
  extra_args=None,
  plus_args=None,
+ pre_cmd=None,
  force_compile=False,
  testcase=None,
  sim_build="sim_build",
@@ -107,6 +108,7 @@ def __init__(
  self.extra_args = some_or(extra_args, [])
  self.simulation_args = some_or(sim_args, [])
  self.plus_args = some_or(plus_args, [])
+ self.pre_cmd = some_or(pre_cmd, [])
  self.force_compile = force_compile
  self.compile_only = compile_only
  self.waves = bool(some_or(waves, int(os.getenv("WAVES", 0))))
@@ -450,6 +452,9 @@ def run_command(self):
  )
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Icarus Verilog.")
+
  verilog_sources = self.verilog_sources_flat.copy()
  if self.waves:
  dump_mod_name = "iverilog_dump"
@@ -502,6 +507,8 @@ def get_parameter_commands(self, parameters):
 
  def do_script(self):
  do_script = ""
+ if self.pre_cmd:
+ do_script += self.pre_cmd
  if self.waves:
  do_script += "log -recursive /*;"
  if not self.gui:
@@ -621,6 +628,8 @@ def get_parameter_commands(self, parameters):
  return parameters_cmd
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Ius.")
 
  assert (
  not self.verilog_compile_args and not self.vhdl_compile_args
@@ -702,6 +711,8 @@ def get_parameter_commands(self, parameters):
  return parameters_cmd
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Xcelium.")
 
  assert (
  not self.verilog_compile_args and not self.vhdl_compile_args
@@ -766,6 +777,8 @@ def get_parameter_commands(self, parameters):
  return [f"-pvalue+{self.toplevel_module}/{name}={str(value)}" for name, value in parameters.items()]
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Vcs.")
 
  pli_cmd = "acc+=rw,wn:*"
 
@@ -831,6 +844,8 @@ def get_parameter_commands(self, parameters):
  return [f"-g{name}={str(value)}" for name, value in parameters.items()]
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for GHDL.")
 
  ghdl_exec = shutil.which("ghdl")
  if ghdl_exec is None:
@@ -924,6 +939,8 @@ def get_parameter_commands(self, parameters):
  return ["-g" + name + "=" + str(value) for name, value in parameters.items()]
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Riviera.")
 
  self.rtl_library = self.toplevel_module
 
@@ -1076,6 +1093,8 @@ def build_script_run(self):
  return "run -all \nexit"
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Activehdl.")
 
  self.rtl_library = self.toplevel_module
 
@@ -1115,6 +1134,8 @@ def get_parameter_commands(self, parameters):
  return [f"-G{name}={str(value)}" for name, value in parameters.items()]
 
  def build_command(self):
+ if self.pre_cmd:
+ print("WARNING: pre_cmd is not implemented for Verilator.")
 
  cmd = []