ice40_hx8k_b_evn

targets/ice40_hx8k_b_evn/base.py

@@ -13,32 +13,81 @@
 from gateware import info
 from gateware import spi_flash
 
+from targets.utils import platform_toolchain_extend
+
 from .crg import _CRG
 
 from litex.soc.cores.uart import UARTWishboneBridge
 
+def round(s):
+    return int(s / 4) * 4
+
 class BaseSoC(SoCCore):
     mem_map = {**SoCCore.mem_map, **{
         'spiflash': 0x20000000,
         'vexriscv_debug': 0xf00f0000,
         'sram': 0,
     }}
+    del mem_map['rom']
 
     def __init__(self, platform, **kwargs):
+
+
+        bios_size = 0x8000
+        spiflash_base = self.mem_map['spiflash']
+        spiflash_bios_base = spiflash_base + platform.gateware_size
+        # Leave a grace area- possible one-by-off bug in add_memory_region?
+        # Possible fix: addr < origin + length - 1
+        spiflash_user_base = spiflash_base + platform.gateware_size + bios_size
+        spiflash_user_size = platform.spiflash_total_size - round(platform.gateware_size + bios_size)
+        print("""
+  Flash start: {:08x}
+Gateware size: {:08x}
+
+   BIOS start: {:08x}
+   BIOS  size: {:08x}
+   BIOS   end: {:08x}
+
+   User start: {:08x}
+   User  size: {:08x}
+   User   end: {:08x}
+
+  Flash   end: {:08x}
+""".format(
+    spiflash_base,
+    platform.gateware_size,
+
+    spiflash_bios_base,
+    bios_size,
+    spiflash_bios_base+bios_size,
+
+    spiflash_user_base,
+    spiflash_user_size,
+    spiflash_user_base+spiflash_user_size,
+
+    spiflash_base + platform.spiflash_total_size,
+))
+
+        kwargs['cpu_reset_address'] = spiflash_bios_base
+
         kwargs['integrated_rom_size']=None
         kwargs['integrated_sram_size']=0x2800
 
-        kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
-
-        # FIXME: Force either lite or minimal variants of CPUs; full is too big.
         kwargs['uart_name'] = 'crossover'
+
         sys_clk_freq = int(12e6)
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
 
+        self.cpu.use_external_variant("gateware/cpu/VexRiscv_Fomu_Debug.v")
+
         self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
         self.add_wb_master(self.uart_bridge.wishbone)
-        self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
+        self.register_mem(
+            name="vexriscv_debug",
+            address=0xf00f0000,
+            interface=self.cpu.debug_bus,
+            size=0x100)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -47,50 +96,65 @@ def __init__(self, platform, **kwargs):
         # Basic peripherals ------------------------------------------------------------------------
         self.submodules.info = info.Info(platform, self.__class__.__name__)
         self.add_csr("info")
-        self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
-        self.add_csr("cas")
+        #self.submodules.cas = cas.ControlAndStatus(platform, sys_clk_freq)
+        #self.add_csr("cas")
 
         # Memory mapped SPI Flash ------------------------------------------------------------------
         self.submodules.spiflash = spi_flash.SpiFlashSingle(
             platform.request("spiflash"),
             dummy=platform.spiflash_read_dummy_bits,
             div=platform.spiflash_clock_div,
-            endianness=self.cpu.endianness)
+            endianness='little') #self.cpu.endianness)
         self.add_csr("spiflash")
         self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
         self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
         self.add_constant("SPIFLASH_TOTAL_SIZE", platform.spiflash_total_size)
-        self.add_wb_slave(
-            self.mem_map["spiflash"],
-            self.spiflash.bus,
-            platform.spiflash_total_size)
-        self.add_memory_region(
-            "spiflash",
-            self.mem_map["spiflash"],
-            platform.spiflash_total_size)
+        self.register_mem(
+            name="spiflash",
+            address=spiflash_base,
+            interface=self.spiflash.bus,
+            size=platform.spiflash_total_size)
 
-        bios_size = 0x8000
+        # BIOS is running from flash
         self.add_constant("ROM_DISABLE", 1)
+        self.soc_mem_map['rom'] = spiflash_bios_base
         self.add_memory_region(
-            "rom", kwargs['cpu_reset_address'], bios_size,
+            name="rom",
+            origin=spiflash_bios_base,
+            length=bios_size,
             type="cached+linker")
-        self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
-        self.add_constant("FLASH_BOOT_ADDRESS", self.flash_boot_address)
+
+        self.flash_boot_address = spiflash_user_base
+        self.add_constant("FLASH_BOOT_ADDRESS", spiflash_user_base)
+
+        # Make the LEDs flash ----------------------------------------------------------------------
+        cnt = Signal(32)
+        self.sync += [
+            cnt.eq(cnt + 1),
+        ]
+        self.comb += [
+            self.platform.request("user_led").eq(cnt[31]),
+            self.platform.request("user_led").eq(cnt[30]),
+            self.platform.request("user_led").eq(cnt[29]),
+            self.platform.request("user_led").eq(cnt[28]),
+            self.platform.request("user_led").eq(cnt[27]),
+            self.platform.request("user_led").eq(cnt[26]),
+            self.platform.request("user_led").eq(cnt[25]),
+        ]
 
         # We don't have a DRAM, so use the remaining SPI flash for user
         # program.
-        #self.add_memory_region("user_flash",
-        #    self.flash_boot_address,
-        #    # Leave a grace area- possible one-by-off bug in add_memory_region?
-        #    # Possible fix: addr < origin + length - 1
-        #    platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
-        #    type="cached+linker")
+        self.soc_mem_map['user_flash'] = spiflash_user_base
+        self.add_memory_region(
+            name="user_flash",
+            origin=spiflash_user_base,
+            length=spiflash_user_size,
+            type="cached+linker")
 
         # Disable final deep-sleep power down so firmware words are loaded
         # onto softcore's address bus.
-        platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
-        platform.toolchain.nextpnr_build_template[1] += " --placer heap"
-        platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
+        platform_toolchain_extend(platform, "icepack", "-s")
+        platform_toolchain_extend(platform, "nextpnr-ice40", "--placer heap")
 
 
 SoC = BaseSoC

targets/ice40_hx8k_b_evn/crg.py

@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+import sys
+import struct
+import os.path
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        clk12 = platform.request("clk12")
+
+        self.clock_domains.cd_sys = ClockDomain()
+        self.reset = Signal()
+
+        # FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr
+        # fixes.
+        self.comb += self.cd_sys.clk.eq(clk12)
+
+        # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
+        # reset.
+        self.clock_domains.cd_por = ClockDomain()
+        reset_delay = Signal(12, reset=4095)
+        self.comb += [
+            self.cd_por.clk.eq(self.cd_sys.clk),
+            self.cd_sys.rst.eq(reset_delay != 0)
+        ]
+        self.sync.por += \
+            If(reset_delay != 0,
+                reset_delay.eq(reset_delay - 1)
+            )
+        self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)