Ice40 HX8K EVB issues #277

niklasnisbeth · 2019-12-30T15:00:44Z

The BIOS does not compare up on the Lattice ice40 HX8K EVB. There are several issues.

I have gotten some of the way here:

niklasnisbeth@846fc61

I have been trying to use litex-buildenv to make a vertexriscv image for the HX8K. I am using the stub firmware. The built firmware does not come up.

We tried adding the UARTWishboneBridge, but wishbone-tool cannot connect to it (as if the Wishbone bus is locking up).

Moving the SRAM to address 0 makes it possible to inspect the wishbone bus with the tool.

The CPU was not running code correctly, changing the SPIFlash to little endian corrects this.

At this point, with UARTWishboneBridge still in, the CPU starts running the BIOS but is stuck in an infinite loop apparently in a call to vsnprintf in the BIOS that I cannot locate.

Removing the UARTWishboneBridge does not make the BIOS come up.

litex-buildenv revision 96ab220 results in a working Micropython environment.

The text was updated successfully, but these errors were encountered:

niklasnisbeth · 2020-01-08T23:06:40Z

Had a little time to dig a bit further into this, I can build a working LM32 firmware until commit da7488c.

From 3a9127d, builds are broken due to memory region stuff that gets fixed in 053ec4d, but at this point the LM32 BIOS does not start.

VexRiscV and Picorv are broken for me even in da7488c - I don't know if that's a separate error to the one that gets introduced in 3a9127d, nor if these builds were ever working on this board. I will focus on LM32 for the the time being since there's a working version to compare to.

3a9127d is rather large, unfortunately. I'll attach debuggers and keep at it as time permits and make notes here.

ewenmcneill · 2020-02-10T01:32:02Z

FTR, it seems like this same issue affects the TinyFPGA BX as well, which has the same iCE40 FPGA chip on it, and the same reliance on execute-in-place from the SPI flash. I've closed #282 in favour of consolidating the discussion here as this issue was opened first (although FTR there's some possibly useful speculation in #282 comments which might be useful for reference).

Ewen

ewenmcneill · 2020-03-05T08:57:30Z

On the TinyFPGA BX front, a month or so back, at the "TimVideos" hackfest, @futaris suggested that one possible reason that the iCE40 8K boards weren't working with newer LiteX is that maybe LiteX had switched to defaulting to Quad-SPI mode, and maybe the TinyFPGA BX (and perhaps the HX8K EVB?) don't support Quad SPI mode.

Tracing tags on the TinyFPGA BX schematic shows that all 6 (non power/ground) pins on the SPI flash are connected to both the iCE40 LP8K and to the underside (inner) "additional pins" connector. These are SCK, SDO, SDI, SS, 82 and 109 on the schematic.

SDO seems to be connected to the iCE40 in two places (H5 / IOB_104_CBSEL1; and G6 / IOB_105_SDO), as is SS connected twice (F8 / IOR_113; and F7 / IOB_108_SS which has a pullup). At a guess SDO is connected twice for dual/quad SPI usage (so one pin can be used in either direction); I'm not sure why SS (chip select for the SPI) is connected twice, possibly it just made the circuit board routing easier?

82 is connected to the FPGA on H4 / IOB_82_GBIN4, and 109 is connected to the FPGA on J8 / IOR_109. Based on the labeling on the TinyFPGA BX back card, 82 is !WP / IO2and 109 is !HOLD / IO3.

So in theory there are enough pins connected between the iCE40 and the SPI flash to to do Quad SPI. The SPI flash seems to be an AT25SF081 which seems to support Quad SPI read. So in theory it'd be possible to make Quad SPI work.

Ewen

ewenmcneill · 2020-03-05T09:18:17Z

The TinyFPGA BX Platform file:

litex-buildenv/platforms/tinyfpga_bx.py

Lines 15 to 28 in e9a1550

    
           ("spiflash", 0, 
        
               Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), 
        
               Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), 
        
               Subsignal("mosi", Pins("G6"), IOStandard("LVCMOS33")), 
        
               Subsignal("miso", Pins("H7"), IOStandard("LVCMOS33")), 
        
               Subsignal("wp", Pins("H4"), IOStandard("LVCMOS33")), 
        
               Subsignal("hold", Pins("J8"), IOStandard("LVCMOS33")) 
        
           ), 
        
           ("spiflash4x", 0, 
        
               Subsignal("cs_n", Pins("F7"), IOStandard("LVCMOS33")), 
        
               Subsignal("clk", Pins("G7"), IOStandard("LVCMOS33")), 
        
               Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33")) 
        
           ),

shows both a spiflash and a spiflash4x config. The spiflash4x dq() line:

litex-buildenv/platforms/tinyfpga_bx.py

Line 27 in e9a1550

Subsignal("dq", Pins("G6 H7 H4 J8"), IOStandard("LVCMOS33"))

is presumably IO0, IO1, IO2, IO3, for which G6, H7, H4, J8 as listed does seem plausible.

The FIXME around the SPI model/size information is a wee bit concerning:

litex-buildenv/platforms/tinyfpga_bx.py

Lines 53 to 59 in e9a1550

    
           # FIXME: Create a "spi flash module" object in the same way we have SDRAM 
        
           spiflash_model = "m25p16" 
        
           spiflash_read_dummy_bits = 8 
        
           spiflash_clock_div = 2 
        
           spiflash_total_size = int((8/8)*1024*1024) # 8Mbit 
        
           spiflash_page_size = 256 
        
           spiflash_sector_size = 0x10000

but it looks like it's been like that for ages, and the information for the iCEBreaker (working) is also similar:

litex-buildenv/platforms/icebreaker.py

Lines 84 to 91 in e9a1550

    
           # FIXME: Create a "spi flash module" object in the same way we have SDRAM 
        
           spiflash_model = "n25q128" 
        
           spiflash_read_dummy_bits = 8 
        
           spiflash_clock_div = 2 
        
           spiflash_total_size = int((128/8)*1024*1024) # 128Mbit 
        
           spiflash_page_size = 256 
        
           # Winbond calls 32kb/64kb sectors "blocks". 
        
           spiflash_sector_size = 0x10000

and also unchanged for ages.

Ewen

ETA: FWIW, the LiteX platform definition doesn't have any of the FIXME SPI additional values:

https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/tinyfpga_bx.py

but otherwise looks basically the same, other than adding a serial port.

Also FWIW, as best I can tell the spiflash_model is only used for determining what to build into the QEMU emulation, at:

litex-buildenv/scripts/build-qemu.sh

Line 120 in e9a1550

    
           SPIFLASH_MODEL=$(grep spiflash_model platforms/$PLATFORM.py | sed -e's/[^"]*"//' -e's/".*$//')

ewenmcneill · 2020-03-05T09:30:45Z

Possibly of note, it looks like the HX8K platform does not have a spiflash4x defined; see https://github.com/timvideos/litex-buildenv/blob/master/platforms/ice40_hx8k_b_evn.py. It only has a single speed SPI interface defined:

litex-buildenv/platforms/ice40_hx8k_b_evn.py

Lines 27 to 32 in e9a1550

    
           ("spiflash", 0, 
        
               Subsignal("cs_n", Pins("R12"), IOStandard("LVCMOS33")), 
        
               Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")), 
        
               Subsignal("mosi", Pins("P12"), IOStandard("LVCMOS33")), 
        
               Subsignal("miso", Pins("P11"), IOStandard("LVCMOS33")), 
        
           ),

(without even !WP or !HOLD). That's also unchanged for years. Presumably if there's no spiflash4x then LiteX just does regular single speed SPI? (Or maybe dual speed SPI?)

Ewen

GitHub
timvideos/litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - timvideos/litex-buildenv

ewenmcneill · 2020-03-05T10:01:23Z

For future reference, these seem to be the changes in the LiteX SPI Master / SPI Flash support that were pulled in by 3a9127d (roughly July 2019 to October 2019), where the relevant commits were found from enjoy-digital/litex@e637aa6...a54b80b (linked as third_party/litex 111 files).

(cd third_party/litex && git diff e637aa65...a54b80b -- litex/soc/cores/spi.py)
(cd third_party/litex && git diff e637aa65...a54b80b -- litex/soc/cores/spi_flash.py)

don't seem to show anything particularly obviously different (including, eg, any default to spiflash4x, so if that changed maybe it's somewhere else).

Ewen

ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log e637aa65...a54b80b -- litex/soc/cores/spi_flash.py
commit 1a6dddd57cf793e09754c11f91acfbb92ce812b6
Author: Sean Cross <sean@xobs.io>
Date:   Fri Sep 20 12:11:59 2019 +0800

    spi_flash: document register fields
    
    Document the various fields present in the SPI flash bitbang interface.
    This adds documentation for the Single and DualQuad modules.
    
    Signed-off-by: Sean Cross <sean@xobs.io>

commit 6d5fddc160ac5778eefe1216f78dc3aa6d526f93
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Wed Aug 14 07:35:45 2019 +0200

    cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally)
ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log e637aa65...a54b80b -- litex/soc/cores/spi.py
commit cca0478a5e57281224fd605078c9f2944ce9ef16
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Mon Sep 16 17:02:55 2019 +0200

    soc/cores/spi: use new CSRField (no functional change)

commit 41fe7cae0b5341531f609943d5f70afd6256cfc8
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Thu Aug 29 09:46:20 2019 +0200

    core/spi: add minimal SPISlave

commit 236070fdcf9d9ef3fec45f046b312e278f2ebe11
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Mon Aug 5 10:36:38 2019 +0200

    cores: -x on spi.py
ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$

ewenmcneill · 2020-03-06T07:27:11Z

I've made an attempt to divide up the large 3a9127d submodule update, to narrow down what's causing the issue with the iCE40 HX8K/TinyFPGA BX. Sort of manually bisecting the submodule updates.

If I check out 3a9127d, do git submodule update --init --recursive, and then do:

cd third_party/litex
git checkout e637aa657b7c1163c7c21c4b972f4aa947406272
git submodule update --init --recursive
cd ../../third_party/litedram
git checkout 6c53996a7042050def908882b36e92585b6ef138

then I can build a working MicroPython on the TinyFPGA BX, even with all the other direct submodules updated (they're mostly not used for MIcroPython on the TinyFPGA BX). Those commits for litex and litedram submodules are the ones from the previous commit, ie before the submodule updates. (It won't build without reverting both litex and litedram, due to Python API compatibility issues AFAICT, hence reverting both.)

So this seems to confirm my hunch that the changes in litex, ie enjoy-digital/litex@e637aa6...a54b80b, is what has broken things. (And I'm reminded by trying to build that commit directly, without reverting litex, that the main change in that range was the memory map handling, including the location of the spiflash / rom / etc changing defaults.)

I'm now going to see if I can narrow down that litex range of commits to less than 3 months worth (2019-07-26 to 2019-10-31) to try to get a closer hint to what might have changed to break things.

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) e
wen@parthenon:/src/fpga/litex-buildenv$ git log -1 | head -6
commit 3a9127d08d8d0be9a68331bd71bf43fc216dbb26
Author: Tim 'mithro' Ansell <me@mith.ro>
Date:   Wed Oct 30 11:39:10 2019 -0700

    Updating submodules.
    
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) e
wen@parthenon:/src/fpga/litex-buildenv$ git submodule
 3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master-21-g3a6108a)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 third_party/flash_proxies (heads/master-2-g01d8f81)
+6c53996a7042050def908882b36e92585b6ef138 third_party/litedram (heads/master-283-g6c53996)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 third_party/liteeth (heads/master-25-g4d9e74f)
 47e76f447f6e3d97aac2638a98f967d44db5c349 third_party/litepcie (remotes/origin/reordering-36-g47e76f4)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 third_party/litesata (heads/master-28-gdb5d2f7)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a third_party/litescope (heads/master-18-g7a9fa9d)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (heads/master-8-g49bafa4)
+e637aa657b7c1163c7c21c4b972f4aa947406272 third_party/litex (heads/master-682-ge637aa65)
 742360f2ba4c400c6164908f03c6ca3d965f168b third_party/litex-renode (heads/master-25-g742360f)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 third_party/migen (0.6.dev-306-g41922fd)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) e
wen@parthenon:/src/fpga/litex-buildenv$

ewenmcneill · 2020-03-06T08:26:50Z

With some experimentation i've been able to get up to litex at the end of 2019-09-29, with litedram at 2019-09-11, and that works okay on the TinyFPGA BX.

Very soon after that (by 2019-09-30 I think) there are some complicated litex / litedram interdependent changes, and I was struggling to even find a combination that would build in that range (because they're clearly interdependent, but there's no actual "this version works with this version" information being maintained for them, so I'm having to guess from dates :-( ).

Anyway, that's narrowed it down to litex/litedram changes between 2019-09-29 and 2019-10-30, a one month range, with about 95 commits in it. AFAICT there are no changes to soc/spi.py or soc/spi_flash.py in that commit range, so I think that rules out SPI being broken somehow.

The main thing that seems to have changed in that range is the entire soft CPU memory architecture... I'm particularly suspicious of the changes starting with enjoy-digital/litex@2c3ad3f, and whatever is the equivalent in litedram (it's moving code from litex to litedram, with a new API, etc).

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log -1
commit 68ba1c60be6d630793541e355c7342c176d2bf08 (HEAD)
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Sat Sep 28 19:04:38 2019 +0200

    soc_core: avoid manual listing of support CPUs, just use CPU.keys()
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ cd ../../third_party/litedram
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litedram$ git log -1
commit f586aada1c5bf00a6fd9e668d129bb36c4006acd (HEAD)
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Wed Sep 11 09:50:46 2019 +0200

    phys: improve presentation (add separators, better indent)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litedram$

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git checkout 68ba1c6 
Previous HEAD position was 4d90058b soc/integration: move cpu_interface retro-compatibility to litex/__init__
HEAD is now at 68ba1c60 soc_core: avoid manual listing of support CPUs, just use CPU.keys()
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log -1
commit 68ba1c60be6d630793541e355c7342c176d2bf08 (HEAD)
Author: Florent Kermarrec <florent@enjoy-digital.fr>
Date:   Sat Sep 28 19:04:38 2019 +0200

    soc_core: avoid manual listing of support CPUs, just use CPU.keys()
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git submodule update --init --recursive
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ cd ..
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party$ cd ..
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv$ make clean
rm -f build/cache.mk
rm -rf build/tinyfpga_bx_base_lm32.minimal/
py3clean . 2>/dev/null || rm -rf $(find -name __pycache__)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv$ 

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git log -1 | head -5
commit 3a9127d08d8d0be9a68331bd71bf43fc216dbb26
Author: Tim 'mithro' Ansell <me@mith.ro>
Date:   Wed Oct 30 11:39:10 2019 -0700

    Updating submodules.
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git submodule
 3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master-21-g3a6108a)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 third_party/flash_proxies (heads/master-2-g01d8f81)
+f586aada1c5bf00a6fd9e668d129bb36c4006acd third_party/litedram (heads/master-319-gf586aad)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 third_party/liteeth (heads/master-25-g4d9e74f)
 47e76f447f6e3d97aac2638a98f967d44db5c349 third_party/litepcie (remotes/origin/reordering-36-g47e76f4)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 third_party/litesata (heads/master-28-gdb5d2f7)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a third_party/litescope (heads/master-18-g7a9fa9d)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (heads/master-8-g49bafa4)
+68ba1c60be6d630793541e355c7342c176d2bf08 third_party/litex (tinyfpga-bx-works-2019-08-10-113-g68ba1c60)
 742360f2ba4c400c6164908f03c6ca3d965f168b third_party/litex-renode (heads/master-25-g742360f)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 third_party/migen (0.6.dev-306-g41922fd)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv$ 

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs Ltd

 BIOS built on Mar  6 2020 21:12:29
 BIOS CRC passed (5e89ec91)

 Migen git sha1: 41922fd
 LiteX git sha1: 68ba1c60

--============ SoC info ================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      10KB

--========= Peripherals init ===========--

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Executing booted program at 0x20058008
--============= Liftoff! ===============--
MicroPython v1.9.4-534-gd2bd40498-dirty on 2020-03-06; litex with lm32
>>> print("Hello World!")
Hello World!
>>>

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log HEAD...a54b80b9b4eaa6defca99b0749da8426535bbb62 | grep "^commit" | wc -l
94
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log HEAD...a54b80b9b4eaa6defca99b0749da8426535bbb62 -- litex/soc/cores/spi.py
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log HEAD...a54b80b9b4eaa6defca99b0749da8426535bbb62 -- litex/soc/cores/spi_flash.py
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-first-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$

ewenmcneill · 2020-03-06T09:05:41Z

enjoy-digital/litex@101f1b1 also builds okay, which is the first 2019-09-30 commit. After that I have to update litedram to 5d1a9847aa805034e58eabf376e2807bfed7b133 to pick up code moved from litex to litedram, and then, I run into AttributeError: 'BaseSoC' object has no attribute 'get_memory_regions', ie, enjoy-digital/litex#290. (The function was apparently removed in enjoy-digital/litex@8be5824#diff-5b5aa398d41ddd6086fbe51e97931f5c to "simplify the code".)

So to carry on testing I need to roll litex-buildenv forward to c9745dc, which works around that API change.

With:

litex-buildenv: c9745dc
litex: enjoy-digital/litex@4d90058
litedram: enjoy-digital/litedram@5d1a984

the combination builds, but I get no serial output any more. So I think that's approximately the first broken version, which seems to confirm that it's the litex/litedram rearrangements that broke things. Ie, the changes on 2019-09-30 seem to be what broke things. There's some other updates trying to fix things up on 2019-10-31 after these changes were merged -- https://github.com/timvideos/litex-buildenv/commits/master?after=e9a1550820dbdf543c62f2f24dd163d12eb403eb+139 -- but it seems like they weren't everything required.

Anyway I've got a strong hunch the issues relate to, eg, memory layout / memory type changes.

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git log -1
commit c9745dc49866e416814716efa41ff10a29819b35 (HEAD -> tinyfpga-bx-2019-10-30-second-broken)
Author: Tim 'mithro' Ansell <me@mith.ro>
Date:   Wed Oct 30 12:19:35 2019 -0700

    make: Updating for new LiteX API.
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git submodule
 3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master-21-g3a6108a)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 third_party/flash_proxies (heads/master-2-g01d8f81)
+5d1a9847aa805034e58eabf376e2807bfed7b133 third_party/litedram (heads/master-328-g5d1a984)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 third_party/liteeth (heads/master-25-g4d9e74f)
 47e76f447f6e3d97aac2638a98f967d44db5c349 third_party/litepcie (remotes/origin/reordering-36-g47e76f4)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 third_party/litesata (heads/master-28-gdb5d2f7)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a third_party/litescope (heads/master-18-g7a9fa9d)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (heads/master-8-g49bafa4)
+4d90058b180ff43856da47f03b7bc736f16b887d third_party/litex (tinyfpga-bx-works-2019-08-10-131-g4d90058b)
 742360f2ba4c400c6164908f03c6ca3d965f168b third_party/litex-renode (heads/master-25-g742360f)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 third_party/migen (0.6.dev-306-g41922fd)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$

ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$ git log | grep "^commit" | grep -B 9999 101f1b
commit 4d90058b180ff43856da47f03b7bc736f16b887d
commit 8be5824e258b84df240d34636aaa539124b92c65
commit 7b72148c4ed6f518397780d77aafe6df70937f9c
commit 63a813af9c53895c9e08e71d132d4bb435ccf8c2
commit 3d257d72665da2ab71a1d651d33e70d76c02a4b8
commit e8e57b4f87b9fc1eb0021b4ab174148fbb112e5b
commit 334ae336bfb98c388d28bc0c03609bdebcf46197
commit 241c3c642bdd1792868a95cf5d8e2e59c8a3d575
commit 48e5a1d14008cb8b33107ce20e9c642be815082a
commit e9ed4761b53160e4f55319bfe7010b380e202e6b
commit 78cecbe36bf2a5d75f2af90d2b3f4d802900cb22
commit 7575ecc6adb07ece0072f609b1eea64b3036725f
commit c6fe3f3145ed77554cc41ce1d8d66df028b7d570
commit 6fcb12a98f6d9df67c5c0390194fc755a300d18f
commit b826c1705f600d0cce6a69ab3b58d9d6b3b2ce8b
commit 355072c285a89286d855d0692800c1ca0d4dd76b
commit 2c3ad3f96d8be73859177d6b51a01fcda06b1f6e
commit 101f1b1cef749aea7d4b1a4897d74868eb77e6c6
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv/third_party/litex$

GitHub
timvideos/litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - timvideos/litex-buildenv

ewenmcneill · 2020-03-06T09:34:11Z

Joy, it looks like enjoy-digital/litex@8be5824 is the commit that removes get_mem_regions(), which means testing anything before that (eg, enjoy-digital/litex@7b72148) means that we have to revert litex-buildenv back to 3a9127d, without the change in c9745dc. Unstable APIs are sooooo much fun when trying to bisect :-(

Looks like working:

litex-buildenv: 3a9127d
litex: enjoy-digital/litex@7b72148
litedram: enjoy-digital/litedram@5d1a984

and failing:

litex-buildenv: c9745dc
litex: enjoy-digital/litex@4d90058
litedram: enjoy-digital/litedram@5d1a984

which are just a few commits apart.

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-third-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git log -1 | head -5
commit 3a9127d08d8d0be9a68331bd71bf43fc216dbb26
Author: Tim 'mithro' Ansell <me@mith.ro>
Date:   Wed Oct 30 11:39:10 2019 -0700

    Updating submodules.
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-third-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git submodule
 3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master-21-g3a6108a)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 third_party/flash_proxies (heads/master-2-g01d8f81)
+5d1a9847aa805034e58eabf376e2807bfed7b133 third_party/litedram (heads/master-328-g5d1a984)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 third_party/liteeth (heads/master-25-g4d9e74f)
 47e76f447f6e3d97aac2638a98f967d44db5c349 third_party/litepcie (remotes/origin/reordering-36-g47e76f4)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 third_party/litesata (heads/master-28-gdb5d2f7)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a third_party/litescope (heads/master-18-g7a9fa9d)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (heads/master-8-g49bafa4)
+7b72148c4ed6f518397780d77aafe6df70937f9c third_party/litex (tinyfpga-bx-works-2019-08-10-129-g7b72148c)
 742360f2ba4c400c6164908f03c6ca3d965f168b third_party/litex-renode (heads/master-25-g742360f)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 third_party/migen (0.6.dev-306-g41922fd)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-third-broken) ewen@parthenon:/src/fpga/litex-buildenv$

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs Ltd

 BIOS built on Mar  6 2020 22:18:06
 BIOS CRC passed (83015cad)

 Migen git sha1: 41922fd
 LiteX git sha1: 7b72148c

--============ SoC info ================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      10KB

--========= Peripherals init ===========--

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Executing booted program at 0x20058008
--============= Liftoff! ===============--
MicroPython v1.9.4-534-gd2bd40498-dirty on 2020-03-06; litex with lm32
>>> print("Hello World!")
Hello World!
>>>

ewenmcneill · 2020-03-06T09:51:38Z

In the interests of science, I've tested the litex commit in the middle -- enjoy-digital/litex@8be5824. As expected, the first failing combination (builds okay, but no output in serial after it is told to boot) is:

litex-buildenv: c9745dc
litex: enjoy-digital/litex@8be5824
litedram: enjoy-digital/litedram@5d1a984

(The litex commit and litex-buildenv commit immediately before that do boot the litex BIOS and MiicroPython just fine; and both of those commits have to be updated together because of an API breakage in litex, as noted in enjoy-digital/litex#290; see #277 (comment) for testing the commits immediately before and after this one.)

Naturally the breaking commit is a huge structural commit in litex that completely rearranges how the memory mapping is handled. My guess is that even with the changes in litex-buildenv (eg, e4c6ffa) that's still not sufficient to get actual XIP (execute in place) from Flash ROM working again :-( And/or it's in a different place now, so it's no longer being compiled to execute in the right location.

@mithro, looks like this is when it failed. But it's going to take more digging (and/or assistance from Florent) to figure out how to make it work again. If you've got any further ideas, they'd be welcomed :-)

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-middle-commit) ewen@parthenon:/src/fpga/litex-buildenv$ git log -1 
commit c9745dc49866e416814716efa41ff10a29819b35 (HEAD -> tinyfpga-bx-2019-10-30-middle-commit, tinyfpga-bx-2019-10-30-second-broken, tinyfpga-bx-2019-10-30-broken-here)
Author: Tim 'mithro' Ansell <me@mith.ro>
Date:   Wed Oct 30 12:19:35 2019 -0700

    make: Updating for new LiteX API.
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-middle-commit) ewen@parthenon:/src/fpga/litex-buildenv$ git submodule
 3a6108a75be356a3dc53760d22782f1323248b6b third_party/edid-decode (heads/master-21-g3a6108a)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 third_party/flash_proxies (heads/master-2-g01d8f81)
+5d1a9847aa805034e58eabf376e2807bfed7b133 third_party/litedram (heads/master-328-g5d1a984)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 third_party/liteeth (heads/master-25-g4d9e74f)
 47e76f447f6e3d97aac2638a98f967d44db5c349 third_party/litepcie (remotes/origin/reordering-36-g47e76f4)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 third_party/litesata (heads/master-28-gdb5d2f7)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a third_party/litescope (heads/master-18-g7a9fa9d)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 third_party/liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 third_party/litevideo (heads/master-8-g49bafa4)
+8be5824e258b84df240d34636aaa539124b92c65 third_party/litex (tinyfpga-bx-works-2019-08-10-130-g8be5824e)
 742360f2ba4c400c6164908f03c6ca3d965f168b third_party/litex-renode (heads/master-25-g742360f)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 third_party/migen (0.6.dev-306-g41922fd)
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-middle-commit) ewen@parthenon:/src/fpga/litex-buildenv$

ewenmcneill · 2020-03-08T03:31:42Z

In case it is useful for reference later, this is the difference in the generated directories between the last working revision combination and the first broken combination. In particular it seems that the SRAM_SIZE has changed, and the FLASH_BOOT_ADDRESS has disappeared from the generated output. The latter is potentially relevant because the TinyFPGA BX target relies on updating the cpu_reset_address so that it can start executing from an address covered by the spiflash memory region; but the generated output may possibly just be an output artifact. (SHADOW_BASE also disappears, but I'm not sure if that's relevant.)

litex-buildenv/targets/tinyfpga_bx/base.py

Line 77 in d6cffe2

    
           kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size+platform.bootloader_size

Also of note, the TinyFPGA BX target is explicitly using single SPI not QuadSPI, so it shouldn't be affected by any QuadSPI default changes anyway:

litex-buildenv/targets/tinyfpga_bx/base.py

Line 87 in d6cffe2

self.submodules.spiflash = spi_flash.SpiFlashSingle(

Ewen

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-just-before-broken) ewen@parthenon:/src/fpga/litex-buildenv$ cp -pr "build/${PLATFORM}_${TARGET}_${CPU}.${CPU_VARIANT}/software/include/generated/" /tmp/tinyfpga-bx-last-working
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-just-before-broken) ewen@parthenon:/src/fpga/litex-buildenv$ diff -r /tmp/tinyfpga-bx-last-working/ /tmp/tinyfpga-bx-first-broken/
diff -r /tmp/tinyfpga-bx-last-working/csr.h /tmp/tinyfpga-bx-first-broken/csr.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 16:18:06
271,278d270
< #define TIMER0_INTERRUPT 1
< static inline int timer0_interrupt_read(void) {
< 	return 1;
< }
< #define UART_INTERRUPT 0
< static inline int uart_interrupt_read(void) {
< 	return 0;
< }
291c283
< #define CAS_LEDS_COUNT 1
---
> #define cas_leds_count 1
295c287
< #define CAS_SWITCHES_COUNT 0
---
> #define cas_switches_count 0
299c291
< #define CAS_BUTTONS_COUNT 0
---
> #define cas_buttons_count 0
315,318c307
< #define CONFIG_CPU_TYPE_LM32 1
< static inline int config_cpu_type_lm32_read(void) {
< 	return 1;
< }
---
> #define CONFIG_CPU_TYPE_LM32
323,326c312
< #define CONFIG_CPU_VARIANT_MINIMAL 1
< static inline int config_cpu_variant_minimal_read(void) {
< 	return 1;
< }
---
> #define CONFIG_CPU_VARIANT_MINIMAL
333a320,331
> }
> #define CONFIG_SHADOW_BASE 2147483648
> static inline int config_shadow_base_read(void) {
> 	return 2147483648;
> }
> #define TIMER0_INTERRUPT 1
> static inline int timer0_interrupt_read(void) {
> 	return 1;
> }
> #define UART_INTERRUPT 0
> static inline int uart_interrupt_read(void) {
> 	return 0;
diff -r /tmp/tinyfpga-bx-last-working/git.h /tmp/tinyfpga-bx-first-broken/git.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 16:18:06
8c8
< #define LITEX_GIT_SHA1 "7b72148c"
---
> #define LITEX_GIT_SHA1 "8be5824e"
diff -r /tmp/tinyfpga-bx-last-working/mem.h /tmp/tinyfpga-bx-first-broken/mem.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 16:18:06
8c8
< #define SRAM_SIZE 0x00002800
---
> #define SRAM_SIZE 0x00004000
21,24d20
< 
< #define FLASH_BOOT_ADDRESS 0x20058000L
< 
< #define SHADOW_BASE 0x80000000L
diff -r /tmp/tinyfpga-bx-last-working/regions.ld /tmp/tinyfpga-bx-first-broken/regions.ld
2c2
< 	sram : ORIGIN = 0x01000000, LENGTH = 0x00002800
---
> 	sram : ORIGIN = 0x01000000, LENGTH = 0x00004000
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-just-before-broken) ewen@parthenon:/src/fpga/litex-buildenv$

ewenmcneill · 2020-03-08T03:57:15Z

So FLASH_BOOT_ADDRESS was removed in the relevant change:

enjoy-digital/litex@8be5824#diff-d35fa8f6bd2523ded61b8e55c30cf6c2L68-L74

There's a bunch of special case code in the litex BIOS boot.c when FLASH_BOOT_ADDRESS is defined:

https://github.com/enjoy-digital/litex/blob/e801dc0261d7101b148135933f441ed82ca61da8/litex/soc/software/bios/boot.c#L361-L371

to do XIP (execute in place) from the spiflash, instead of copying into RAM. So if FLASH_BOOT_ADDRESS is not defined, that special case handling presumably won't be triggered any more.

AFAICT this relates to the handling of the application (eg, MicroPython) rather than the BIOS itself. So I think we should still be getting BIOS messages on the serial before that, and we're getting nothing on the serial interface when it fails. Which implies not even the BIOS is running.

But noting this because even if we get the BIOS to run, there might still need to be more work done to be able to do XIP of MicroPython again....

Ewen

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

ewenmcneill · 2020-03-08T04:26:31Z

Of note, the lm32-crt0.S also has EXECUTE_IN_PLACE special cases:

https://github.com/enjoy-digital/litex/blob/e801dc0261d7101b148135933f441ed82ca61da8/litex/soc/software/libbase/crt0-lm32.S#L115-L131

which is triggered by using crt0-lm32-xip.o:

https://github.com/enjoy-digital/litex/blob/e801dc0261d7101b148135933f441ed82ca61da8/litex/soc/software/libbase/Makefile#L30-L31

And which one is used (lm32-crt0-xip.o / lm32-crt0-ctr.o) determines whether the BIOS will be executed in place (xip) or Copied to RAM (ctr). In litex-buildenv, this is controlled by the COPY_TO_RAM define:

litex-buildenv/firmware/Makefile

Lines 69 to 75 in d6cffe2

    
           ifeq ($(COPY_TO_MAIN_RAM), 1) 
        
           CRT0 = ../libbase/crt0-$(CPU)-ctr.o 
        
           LINKER_LD = linker-ctr.ld 
        
           else 
        
           CRT0 = ../libbase/crt0-$(CPU)-xip.o 
        
           LINKER_LD = linker-xip.ld 
        
           endif

which seems to come from the generated variables.mak:

litex-buildenv/firmware/Makefile

Line 1 in d6cffe2

include ../include/generated/variables.mak

but those variables haven't actually changed between the working and broken versions:

ewen@parthenon:/tmp/tinyfpga-bx-last-working$ egrep "EXECUTE|COPY" variables.mak 
COPY_TO_MAIN_RAM=0
EXECUTE_IN_PLACE=1
ewen@parthenon:/tmp/tinyfpga-bx-last-working$

ewen@parthenon:/tmp/tinyfpga-bx-first-broken$ egrep "EXECUTE|COPY" variables.mak
COPY_TO_MAIN_RAM=0
EXECUTE_IN_PLACE=1
ewen@parthenon:/tmp/tinyfpga-bx-first-broken$

Anyway since crt0 runs before main() in the BIOS, if there's an issue here, then it'll prevent main() from even starting, which plausibly causes the symptoms experienced.

The main other thing which jumps out as before output in main() is the UART init, which depends on setting up interrupts, etc. So anything breaking the UART handling would also cause no output.

https://github.com/enjoy-digital/litex/blob/e801dc0261d7101b148135933f441ed82ca61da8/litex/soc/software/bios/main.c#L575-L589

Ewen

PS: AFAICT few other CPU start.S entries have special cases for EXECUTE_IN_PLACE so this might mean that the smaller iCE40 boards are limited to using the lm32 soft CPU to get this handling.

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

ewenmcneill · 2020-03-08T06:30:08Z

FTR, I've figured out where the sram size is being changed from 0x2800 to 0x4000, and I think it's probably a mistake. (Or at least if it's being done deliberately, it's the weirdest undocumented side effect.)

As a reminder this is the relevant difference in the memory map between the working commit and the broken commit:

ewen@parthenon:/tmp$ diff tinyfpga-bx-last-working/regions.ld tinyfpga-bx-first-broken/regions.ld 
2c2
< 	sram : ORIGIN = 0x01000000, LENGTH = 0x00002800
---
> 	sram : ORIGIN = 0x01000000, LENGTH = 0x00004000
ewen@parthenon:/tmp$

and I assume that the actual soft hardware space is 0x2800 in size (approx 10k) rather than 0x4000(16k) in size, because the iCE40 8k is pretty RAM constrained and the relevant platforms have no external ("main") RAM.

It happens at :

https://github.com/enjoy-digital/litex/blob/8be5824e258b84df240d34636aaa539124b92c65/litex/soc/integration/soc_core.py#L355

(which has been rearranged again in subsequent commits), where r.length, ie the SocMemRegion object's length value is maniuplated as part of calculating if there are overlapping memory ranges being defined.

FTR, I believe it's using the Migen log2_int definition:

https://github.com/m-labs/migen/blob/3f9809b0ea62b26f6c99f1b5221b22f8255bc1f6/migen/fhdl/bitcontainer.py#L7-L13

Given those length values end up in the linker map, it seems to me unsafe to go around updating the length after it's been defined, and my guess is that it wasn't intended to do so. The previous code did change the same variable, but it wasn't referencing into an object so I think it'd just have bound a local copy of that variable instead. See:

enjoy-digital/litex@8be5824#diff-5b5aa398d41ddd6086fbe51e97931f5cL352-R358

for what changed.

My guess is that this "accidentally worked" before, and got broken by the refactoring, resulting in a new linker map, which potentially resulted in trying to reference RAM that doesn't exist.

And a bunch of the LM32 exception handlers are basically just "lock up":

https://github.com/enjoy-digital/litex/blob/e801dc0261d7101b148135933f441ed82ca61da8/litex/soc/software/libbase/crt0-lm32.S#L26-L108

so if the compiler happens to, eg, try to put the stack at the top of the (newly expanded) RAM range, which isn't backed by anything, I suspect it'll all go terribly wrong the first time the stack is used :-(

So current'y that's my strongest theory for what went wrong with this commit.

Ewen

time python -u ./make.py --platform=tinyfpga_bx --target=base --cpu-type=lm32 --iprange=192.168.100   --cpu-variant=minimal --cpu-variant=minimal  \
	2>&1 | tee -a /src/fpga/litex-buildenv/build/tinyfpga_bx_base_lm32.minimal//output.20200308-190704.log; (exit ${PIPESTATUS[0]})
Setting integrated RAM size: 00002800
> /src/fpga/litex-buildenv/targets/tinyfpga_bx/base.py(82)__init__()
-> SoCCore.__init__(self, platform, clk_freq, **kwargs)
(Pdb) b litex/soc/integration/soc_core.py:208
Breakpoint 1 at /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py:208
(Pdb) c
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(208)__init__()
-> if integrated_sram_size:
(Pdb) print(integrated_sram_size)
10240
(Pdb) n
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(209)__init__()
-> self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
(Pdb) n
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(210)__init__()
-> self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
(Pdb) n
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(213)__init__()
-> if integrated_main_ram_size:
(Pdb) print(integrated_sram_size)
10240
(Pdb) print(self.mem_regions['sram'].length)
10240
(Pdb) b litex/soc/integration/soc_core.py:354
Breakpoint 2 at /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py:354
(Pdb) c
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(354)add_memory_region()
-> for n, r in self.mem_regions.items():
(Pdb) print(self.mem_regions['sram'].length)
10240
(Pdb) n
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(355)add_memory_region()
-> r.length = 2**log2_int(r.length, False)
(Pdb) print(n)
sram
(Pdb) print(r.length)
10240
(Pdb) n
> /src/fpga/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py(356)add_memory_region()
-> if n == name or in_this_region(r.origin) or in_this_region(r.origin + r.length - 1):
(Pdb) print(r.length)
16384
(Pdb) ^C
real	2m49.107s
user	0m0.171s
sys	0m0.008s
Makefile:266: recipe for target 'gateware' failed
make: *** [gateware] Error 1

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

GitHub
m-labs/migen
A Python toolbox for building complex digital hardware - m-labs/migen

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

ewenmcneill · 2020-03-08T07:11:36Z

The litex code got changed a couple of times on 2019-10-29:

enjoy-digital/litex@4014fbf
enjoy-digital/litex@9fcf297

The first still adjusts other memory regions when checking, but it seems to me that the second one pre-adjusts the length when adding a region so won't adjust a region length later.

Unfortunately by the time we reach that commit, the sram is being added via add_memory_region, which means that it has its size adjusted up to the next power of 2 boundary before it is added (rather than after):

https://github.com/enjoy-digital/litex/blob/9fcf29738710f755ed45ad967eacd2287cd91a67/litex/soc/integration/soc_core.py#L392-L406

so the net effect is the same I think -- the sram size will be increased from 0x2800 to 0x4000.

By the next change to this function:

enjoy-digital/litex@53bc18c

there's actually a comment explaining that it's rounding the size up to the next power of 2, but it's still rounding up.

Then there's another huge refactoring 2020-02-06:

enjoy-digital/litex@6baa07a

which makes tracing the changes even harder ;-( I think that address decoder then relies on sizes being powers of 2:

enjoy-digital/litex@6baa07a#diff-d0cf5288909863f45f2189bab58b6abeR38-R67

but it's not clear how that propagates out to generated linker/include files (at least from looking at the diff).

Possibly that later version actually does the correct thing: ie, retains the memory region size as it was requested, but arranges the memory map so that things are powers-of-2 separated (for easy address decoding). So that the compiler will only use the validly mapped ram, but the address decoding is also a simple bitmask. I'm not sure if we have a February 2020-ish version to test.

But anyway the other obvious thing to try testing is just reducing the sram size to 0x2000 (from 0x2800), ie to 8kB (from 10kB), so that it's a power of 2. I'm not actually sure if that's going to be enough RAM to boot anything, but it at least seems worth a try.

Ewen

GitHub
enjoy-digital/litex
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ewenmcneill · 2020-03-08T07:23:50Z

\o/

8kB 0x2000 RAM works with the newer (first broken) commits. It doesn't boot to MicroPython, only to the BIOS, because it can't find anything to boot from, but that's a separate problem (#277 (comment)). At least we now know why it wasn't even booting into the BIOS at all.

I think at this point I file a litex issue to see whether any of this is even still supported any more, or if the entire TinyFPGA platform port (ie, XIP) has been deliberately thrown out.

Ewen

python -m litex.soc.software.mkmscimg -f build/tinyfpga_bx_base_lm32.minimal//software/micropython/firmware.bin -o build/tinyfpga_bx_base_lm32.minimal//software/micropython/firmware.fbi
python mkimage.py \
	  --cpu-variant=minimal --cpu-variant=minimal \
	--override-gateware=build/tinyfpga_bx_base_lm32.minimal//gateware/top.bin \
	--override-bios=build/tinyfpga_bx_base_lm32.minimal//software/bios/bios.bin \
	--override-firmware=build/tinyfpga_bx_base_lm32.minimal//software/micropython/firmware.fbi \
	--output-file=build/tinyfpga_bx_base_lm32.minimal//image-gateware+bios+micropython.bin

Gateware @ 0x00000000 (    135100 bytes) build/tinyfpga_bx_base_lm32.minimal//gateware/top.bin        - Xilinx FPGA Bitstream
ff 00 00 ff 7e aa 99 7e 51 00 01 05 92 00 21 62 03 67 72 01 10 82 00 00 11 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    BIOS @ 0x00028000 (     16004 bytes) build/tinyfpga_bx_base_lm32.minimal//software/bios/bios.bin  - LiteX BIOS with CRC
98 00 00 00 d0 00 00 00 78 01 20 05 38 21 00 00 d0 e1 00 00 e0 00 00 3b 34 00 00 00 34 00 00 00 e0 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00
Firmware @ 0x00030000 (    245076 bytes) build/tinyfpga_bx_base_lm32.minimal//software/micropython/firmware.fbi - HDMI2USB Firmware in FBI format (loaded into DRAM)
00 03 bd 4c 83 49 01 b2 98 00 00 00 d0 00 00 00 78 01 20 05 38 21 80 08 d0 e1 00 00 e0 00 00 3b 34 00 00 00 34 00 00 00 e0 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00 34 00 00 00
----------------------------------------
       Remaining space     606892 bytes (4 Megabits, 0.58 Megabytes)
           Total space    1048576 bytes (8 Megabits, 1.00 Megabytes)

Flash image: build/tinyfpga_bx_base_lm32.minimal//image-gateware+bios+micropython.bin
ff 00 00 ff 7e aa 99 7e 51 00 01 05 92 00 21 62 03 67 72 01 10 82 00 00 11 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
tinyprog  --program-image build/tinyfpga_bx_base_lm32.minimal//image-gateware+bios+micropython.bin

    TinyProg CLI
    ------------
    Using device id 1d50:6130
    Only one board with active bootloader, using it.

    Programming /dev/ttyACM0 with build/tinyfpga_bx_base_lm32.minimal//image-gateware+bios+micropython.bin
    Programming at addr 028000
    Waking up SPI flash
    441684 bytes to program
    Programming and Verifying: 442kB [00:04, 98.9kB/s]                                                                                       
    Success!

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ diff /tmp/tinyfpga-bx-last-working/ build/tinyfpga_bx_base_lm32.minimal/software/include/generated/
diff /tmp/tinyfpga-bx-last-working/csr.h build/tinyfpga_bx_base_lm32.minimal/software/include/generated/csr.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 20:16:49
271,278d270
< #define TIMER0_INTERRUPT 1
< static inline int timer0_interrupt_read(void) {
< 	return 1;
< }
< #define UART_INTERRUPT 0
< static inline int uart_interrupt_read(void) {
< 	return 0;
< }
291c283
< #define CAS_LEDS_COUNT 1
---
> #define cas_leds_count 1
295c287
< #define CAS_SWITCHES_COUNT 0
---
> #define cas_switches_count 0
299c291
< #define CAS_BUTTONS_COUNT 0
---
> #define cas_buttons_count 0
315,318c307
< #define CONFIG_CPU_TYPE_LM32 1
< static inline int config_cpu_type_lm32_read(void) {
< 	return 1;
< }
---
> #define CONFIG_CPU_TYPE_LM32
323,326c312
< #define CONFIG_CPU_VARIANT_MINIMAL 1
< static inline int config_cpu_variant_minimal_read(void) {
< 	return 1;
< }
---
> #define CONFIG_CPU_VARIANT_MINIMAL
333a320,331
> }
> #define CONFIG_SHADOW_BASE 2147483648
> static inline int config_shadow_base_read(void) {
> 	return 2147483648;
> }
> #define TIMER0_INTERRUPT 1
> static inline int timer0_interrupt_read(void) {
> 	return 1;
> }
> #define UART_INTERRUPT 0
> static inline int uart_interrupt_read(void) {
> 	return 0;
diff /tmp/tinyfpga-bx-last-working/git.h build/tinyfpga_bx_base_lm32.minimal/software/include/generated/git.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 20:16:49
8c8
< #define LITEX_GIT_SHA1 "7b72148c"
---
> #define LITEX_GIT_SHA1 "8be5824e"
diff /tmp/tinyfpga-bx-last-working/mem.h build/tinyfpga_bx_base_lm32.minimal/software/include/generated/mem.h
2c2
< // Auto-generated by Migen (41922fd) & LiteX (7b72148c) on 2020-03-08 16:21:45
---
> // Auto-generated by Migen (41922fd) & LiteX (8be5824e) on 2020-03-08 20:16:49
8c8
< #define SRAM_SIZE 0x00002800
---
> #define SRAM_SIZE 0x00002000
21,24d20
< 
< #define FLASH_BOOT_ADDRESS 0x20058000L
< 
< #define SHADOW_BASE 0x80000000L
diff /tmp/tinyfpga-bx-last-working/regions.ld build/tinyfpga_bx_base_lm32.minimal/software/include/generated/regions.ld
2c2
< 	sram : ORIGIN = 0x01000000, LENGTH = 0x00002800
---
> 	sram : ORIGIN = 0x01000000, LENGTH = 0x00002000
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ git diff targets/
diff --git a/targets/tinyfpga_bx/base.py b/targets/tinyfpga_bx/base.py
index 9ab8bd2..cfeffdf 100755
--- a/targets/tinyfpga_bx/base.py
+++ b/targets/tinyfpga_bx/base.py
@@ -66,7 +66,9 @@ class BaseSoC(SoCCore):
         if 'integrated_rom_size' not in kwargs:
             kwargs['integrated_rom_size']=0
         if 'integrated_sram_size' not in kwargs:
-            kwargs['integrated_sram_size']=0x2800
+            # 2020-03-08 - Litex memory regions now need to be powers of 2
+            #kwargs['integrated_sram_size']=0x2800
+            kwargs['integrated_sram_size']=0x2000
 
         # FIXME: Force either lite or minimal variants of CPUs; full is too big.
 
(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ ^C

(LX P=tinyfpga_bx.minimal F=micropython R=tinyfpga-bx-2019-10-30-second-broken) ewen@parthenon:/src/fpga/litex-buildenv$ make firmware-connect
flterm --port=/dev/ttyUSB0 --speed=115200
[FLTERM] v2.4-29-g47d3b15 Starting...

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|

 (c) Copyright 2012-2019 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs Ltd

 BIOS built on Mar  8 2020 20:16:49
 BIOS CRC passed (0109b767)

 Migen git sha1: 41922fd
 LiteX git sha1: 8be5824e

--============ SoC info ================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      8KB

--========= Peripherals init ===========--

--========== Boot sequence =============--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--
litex>

ewenmcneill · 2020-03-08T08:11:41Z

@niklasnisbeth I've CC'd you (and @mithro) on enjoy-digital/litex#417; hope that's okay.

@niklasnisbeth If you do have a way of trying the iCE40 HK8K with the sram size forced to 0x2000 (8kB) instead of 0x2800 (10kB) I think that'd be a useful thing to do. In theory it should at least show the Litex boot messages and confirm that serial output works for you too.

Ewen

ewenmcneill · 2020-03-13T07:27:49Z

FTR, the default integrated_sram_size is coming from litex soc_core.py:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L266-L268

and is also repeated at:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L71-L72

both with hard coded values (I'm not sure why it doesn't follow DRY).

These arguments are included via:

https://github.com/timvideos/litex-buildenv/blob/master/make.py#L15

and:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_sdram.py#L53-L54

And approximately the same for integrated_rom_size, but one of them is set to 0:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L68-L70

and one of them is set to 32kB:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L261-L265

for added confusion.

Anyway this means it's now harder to distinguish "user specified the default value explicitly" from "user allowed the value to default", than it was when the defaults were 0 so you could be pretty certain if they were specified they were from the user :-(

FWIW, for reasons I don't understand litex-buildenv make.py calls soc_sdram_args(parser) in two places:

litex-buildenv/make.py

Line 15 in d6cffe2

soc_sdram_args(parser)

litex-buildenv/make.py

Line 117 in d6cffe2

soc_sdram_args(parser)

and it seems like it'll be called both times every run :-(

It's not clear to me if that's just an oversight, or there's something trying to be done by readding the same arguments....

Ewen

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

GitHub
timvideos/litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - timvideos/litex-buildenv

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

ewenmcneill · 2020-03-13T07:34:46Z

both with hard coded values (I'm not sure why it doesn't follow DRY).

Ah, now I look at the locations, one is the __init__() default arguments, and one is the parser setup. I do still think it'd be a better idea to have a shared common table of "default defaults" both of those were set from... (and in that same comment I asked whether the integrated_rom_size difference was intentional).

Ewen

ewenmcneill · 2020-03-13T07:50:10Z

The arguments to the target come via:

litex-buildenv/make.py

Lines 55 to 57 in d6cffe2

    
           def get_soc(args, platform): 
        
               exec("from targets.{}.{} import SoC".format(args.platform, args.target.lower(), args.target), globals()) 
        
               soc = SoC(platform, ident=SoC.__name__, **soc_sdram_argdict(args), **dict(args.target_option))

which filters out the command line parsed args via:

https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_sdram.py#L65-L72
https://github.com/enjoy-digital/litex/blob/b5bddc2332bc701fbcfe028faf0980a3e6641320/litex/soc/integration/soc_core.py#L300-L314

and turns it into a pair of dicts which are mashed into **kwargs that just contain the "relevant" arguments.

So by that point it's no longer possible to get at the argparse object and, eg, find out what the default values were for those potential options. Nor is it possible without changing a non-trivial amount of code to, eg, pass another set of values in that contain the "defaults", or indicate which ones were set on the command line and which ones were just allowed to default.

And the "default defaults" aren't anywhere particularly convenient either, so we (a) can't trivially have per-target defaults (the SoC target isn't known until after the command line arguments are parsed), and (b) we can't even compare the value we got with the known defaults to find out if it's at least different.

About the only thing I can think of to do is to try setting per target defaults via the target Makefile, and then do something like what is done with the CPU:

litex-buildenv/make.py

Lines 15 to 17 in d6cffe2

    
           soc_sdram_args(parser) 
        
           parser.set_defaults(cpu_type=os.environ.get('CPU', 'lm32')) 
        
           parser.set_defaults(cpu_variant=os.environ.get('CPU_VARIANT', None) or None)

which might actually be overwritten by the second call to soc_sdram_args(parser) later in main() anyway....

Otherwise we unconditionally force the sram / rom sizes for the targets in the target base.py and accept it can't be changed anywhere else.

Ewen

GitHub
enjoy-digital/litex
Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

* edid-decode changed from 42f5fa4 to 3a6108a * 3a6108a - edid-decode: Add Dell UP3218K DP tiled edid <Clint Taylor> * ad20c30 - edid-decode: improve DisplayID 1.2/3 parsing <Hans Verkuil> * 31a3417 - edid-decode: add warn() function <Hans Verkuil> * 8752afd - edid-decode: improve some of the texts <Hans Verkuil> * 8f7bb1f - edid-decode: improve readability of output <Hans Verkuil> * dc8afbf - edid-decode: add new HDMI 2.1 Amendment A1 and HDR10+ support <Hans Verkuil> * 44d1587 - edid-decode: add more EDIDs <Hans Verkuil> * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil> * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao> * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil> * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil> * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil> * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil> * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil> * flash_proxies changed from 1c21ee4 to 01d8f81 * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq> * litedram changed from 6c53996 to 401554f * 401554f - Merge pull request timvideos#92 from gsomlo/gls-assert-width <enjoy-digital> |\ | * 7356d3b - frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native <Gabriel Somlo> | * 24203cf - frontend/axi: add assertion on matching axi, native port data_width <Gabriel Somlo> |/ * d84e1b4 - frontend/axi: add assert on axi.address_width and base_address <Florent Kermarrec> * 1d037d2 - frontend/axi: add base_address parameter to LiteDRAMAXI2Native <Florent Kermarrec> * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec> * d647abd - gen: fix with_wishbone <Florent Kermarrec> * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec> * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec> * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec> * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec> * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt> * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt> * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec> * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec> * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec> * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec> * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec> * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec> * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec> * 40b4c62 - test/test_init: fix <Florent Kermarrec> * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec> * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec> * 6e176d4 - init: split by memtype <Florent Kermarrec> * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec> * bf5883c - rename sdram_init to init <Florent Kermarrec> * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec> * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec> * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec> * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec> * 00ecb87 - gen: add separators <Florent Kermarrec> * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec> * f678efa - travis: add pyyaml <Florent Kermarrec> * 8861d80 - Merge pull request timvideos#91 from sd-fritze/master <enjoy-digital> |\ | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf> |/ * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec> * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec> * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec> * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec> * 602ff8b - examples: switch to YAML config files <Florent Kermarrec> * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec> * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec> * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec> * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec> * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec> * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec> * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec> * f0592ff - core/refresher: add comments <Florent Kermarrec> * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec> * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec> * liteeth changed from ad187d3 to 4d9e74f * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec> * 4bc79ce - examples/targets/core: update <Florent Kermarrec> * cd0eaa9 - Merge pull request timvideos#19 from jersey99/master <enjoy-digital> * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla> * litepcie changed from 71c9a3a to 47e76f4 * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec> * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec> * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec> * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec> * litescope changed from 9e3b9d8 to 7a9fa9d * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec> * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec> * 69a8df0 - Merge pull request timvideos#14 from DurandA/master <enjoy-digital> * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand> * litevideo changed from 98e145f to 49bafa4 * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec> * litex changed from v0.1-1099-ge637aa65 to v0.1-1333-ga54b80b9 * a54b80b9 - targets: use type="io" instead of io_region=True <Florent Kermarrec> * a0c0a6fd - integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json <Florent Kermarrec> * 9fcf2973 - soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) <Florent Kermarrec> * 4014fbff - soc_core/add_memory_region: fix memory overlap detection <Florent Kermarrec> * 650df0eb - test/test_targets: skip Minerva test on Travis-CI, remove commented tests <Florent Kermarrec> * ab8af282 - cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier <Florent Kermarrec> * 4cc40aad - Merge pull request timvideos#286 from gsomlo/gls-timingstrict <enjoy-digital> |\ | * 49372852 - build/lattice/trellis: optionally allow failure if p&r timing not met <Gabriel Somlo> |/ * b6d35c92 - Merge pull request timvideos#283 from kbeckmann/kbeckmann/bios_increment_address <enjoy-digital> |\ | * ef78ae95 - bios: Increment address when writing to flash <Konrad Beckmann> * | 683e0668 - build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met <Florent Kermarrec> * | 4cf346a1 - soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 <Florent Kermarrec> * | 39862f06 - Merge pull request timvideos#282 from antmicro/icapbitstream_fixes <enjoy-digital> |\ \ | * | 8b5da9c6 - cores/icap/ICAPBitstream: add source ready signal. <Jan Kowalewski> |/ / * | 626533ce - soc/integration/__init__: remove imports (not used and causing issues <Florent Kermarrec> * | 675b4552 - build: always use platform.add_source and avoid manipulate platform.sources directly <Florent Kermarrec> * | 43f5d1ef - build/generic_platform: replace set with list for sources/verilog_include_paths <Florent Kermarrec> * | 97a77b95 - cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. <Florent Kermarrec> * | 98c224be - build/generic_platform: keep language to None if None after tools.language_by_filename <Florent Kermarrec> * | 14dae8bd - soc_core: fix default --uart_name <Florent Kermarrec> * | ba264418 - integration/soc_core: expose more SoC parameters <Florent Kermarrec> * | 23d83961 - Merge pull request timvideos#280 from kbeckmann/picorv32_typo <Tim Ansell> |\ \ | |/ |/| | * 0e467168 - picorv32: Fix minimal variant params <Konrad Beckmann> |/ * ef504f62 - soc_core: fix soc_core_argdict <Florent Kermarrec> * cd8213b9 - cpu/lm32: add missing buses <Florent Kermarrec> * 5a035875 - soc_core/soc_core_argdict: use inspect to get all parameters and simplify <Florent Kermarrec> * 96c369f3 - integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) <Florent Kermarrec> * 29e51f5e - interconnect/wishbone: fix Converter case when buses are identical <Florent Kermarrec> * ae9c25b7 - platforms/versa_ecp5: add serdes refclk/sma <Florent Kermarrec> * 9a829338 - cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) <Florent Kermarrec> * ca81cc20 - soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) <Florent Kermarrec> * 03faf06c - soc/interconnect/axi: re-align to improve readability <Florent Kermarrec> * 7dea9afd - software/bios: simplify banners <Florent Kermarrec> * 6bd18893 - cpu/picorv32: remove obsolete comment <Florent Kermarrec> * 28517d20 - cpu/picorv32: use a single idbus <Florent Kermarrec> * 5daf1a22 - cpu: cleanup/re-align <Florent Kermarrec> * 467d35ed - cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix <Florent Kermarrec> * 1045cda3 - cpu: add buses list and use it in soc_core to add bus masters <Florent Kermarrec> * 42ccc91f - integration: move soc constants to soc.h of csr.h <Florent Kermarrec> * ed3c53d7 - build/generic_platform: only add sources if language is not None <Florent Kermarrec> * f3ba0788 - xilinx/vivado: replace "xy" == language with language == "xy" <Florent Kermarrec> * 17756f63 - Merge pull request timvideos#277 from railnova/feature/vivado_sysverilog_support <enjoy-digital> |\ | * f2369a4c - Add system Verilog support for the Vivado builder <Martin Cornil> * | b2519482 - integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) <Florent Kermarrec> * | 496ba7e5 - bios/main: use same banner than README (MiSoC cited in README/LICENSE) <Florent Kermarrec> * | 840f01b6 - software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf <Florent Kermarrec> |/ * 37531cec - Merge pull request timvideos#276 from gsomlo/gls-rocket-map <enjoy-digital> |\ | * f8f643a0 - cpu/rocket: swap main_mem and io regions <Gabriel Somlo> |/ * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec> * cc245fc8 - Merge pull request timvideos#275 from pcotret/patch-1 <enjoy-digital> |\ | * e923a88d - Update README (related to issue timvideos#273) <Pascal Cotret> * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec> * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec> * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec> * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec> * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec> |/ * e8b90e80 - Merge pull request timvideos#274 from gsomlo/gls-shadow-base <enjoy-digital> |\ | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo> |/ * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec> * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec> * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec> * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec> * 2dfe7441 - Merge pull request timvideos#271 from gsomlo/gls-yosys-nowidelut <enjoy-digital> |\ | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo> * | c954ff0c - Merge pull request timvideos#272 from sergachev/fix-comments <enjoy-digital> |\ \ | |/ |/| | * 2f7bd971 - fix comments <Ilia Sergachev> * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec> |/ * 960b25a5 - Merge pull request timvideos#270 from gsomlo/gls-csr-upper <enjoy-digital> |\ | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo> * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec> * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec> * | 4bb2827e - Merge pull request timvideos#269 from antmicro/rework_icap <enjoy-digital> |\ \ | |/ |/| | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski> * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec> * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec> * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec> * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec> * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec> * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec> * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec> * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec> * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec> * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec> * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec> * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec> * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec> * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec> * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec> * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec> * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec> * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec> * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec> * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec> * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec> * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec> * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec> * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec> * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec> * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec> * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec> * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec> * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec> * | a4069fc8 - add SERV submodule <Florent Kermarrec> * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec> * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec> * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec> * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec> * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec> * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec> * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec> * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec> * | 836d5b88 - Merge pull request timvideos#266 from xobs/add-moduledoc-autodoc <enjoy-digital> |\ \ | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross> | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross> * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec> * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt> * | | 742da31b - Merge pull request timvideos#264 from antmicro/mor1kx_linux <enjoy-digital> |\ \ \ | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski> | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski> * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec> * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec> |/ / / * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec> * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec> * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec> * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec> * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt> * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt> * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt> |/ / * | 8b7d8217 - Merge pull request timvideos#263 from xobs/spi-flash-csrfield <enjoy-digital> |\ \ | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross> |/ / * | 4f659ba4 - Merge pull request timvideos#262 from jersey99/master <enjoy-digital> |\ \ | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla> |/ / * | 430fee4d - Merge pull request timvideos#261 from xobs/event-documentation <enjoy-digital> |\ \ | |/ |/| | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross> |/ * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec> * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec> * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec> * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec> * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec> * f1139c36 - Merge pull request timvideos#259 from xobs/document-timer <enjoy-digital> |\ | * cb7d941a - timer: add documentation <Sean Cross> |/ * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec> * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec> * 3dc8d294 - Merge pull request timvideos#257 from enjoy-digital/csr_fields <enjoy-digital> |\ | * 9bda614a - csr: update copyrights <Florent Kermarrec> | * 29134cc6 - csr: more documentation <Florent Kermarrec> | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec> | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec> | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec> | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec> | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec> | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec> | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec> |/ * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec> * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec> * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec> * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec> * cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * a7b5c185 - Merge pull request timvideos#255 from sergachev/fix-crc32 <enjoy-digital> | |\ | | * 2400f0f4 - fix crc32 <Ilia Sergachev> | |/ * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec> |/ * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec> * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec> * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec> * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec> * 2638393b - soc_zynq: fix indent <Florent Kermarrec> * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec> * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec> * 6f150a56 - Merge pull request timvideos#254 from mithro/crc-smaller <enjoy-digital> |\ | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell> | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell> | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross> | * a59d0efc - libbase: crc32: add smaller version <Sean Cross> * | 27c334d4 - Merge pull request timvideos#252 from mithro/only-change-on-contents <Tim Ansell> |\ \ | |/ |/| | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell> |/ * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec> * 19d3acfc - Merge pull request timvideos#251 from micro-FPGA/master <enjoy-digital> |\ | * fb00ee85 - Create atlantic.py <Antti Lukats> | * 92e5b4b2 - Merge pull request timvideos#2 from enjoy-digital/master <Antti Lukats> | |\ | * | f47e4978 - libero enable enhanced constraints <Antti Lukats> * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec> * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec> * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec> * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec> * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec> * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec> * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec> * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec> * | | d79cd87d - Merge pull request timvideos#246 from gsomlo/gls-native-rv64 <enjoy-digital> |\ \ \ | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo> |/ / / * | | d36f1fb7 - Merge pull request timvideos#244 from atommann/master <enjoy-digital> |\ \ \ | |_|/ |/| | | * | a45dbee5 - changing http to https <atommann> | * | 1d957d7a - Update .gitmodules <atommann> * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec> * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats> | |/ |/| * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec> * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec> * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec> * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec> * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec> * | f6638ded - Merge pull request timvideos#243 from sergachev/master <enjoy-digital> |\ \ | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev> * | | ccc2cbd9 - Merge pull request timvideos#241 from railnova/zynq <enjoy-digital> |\ \ \ | |/ / |/| | | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset> |/ / * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec> * | 383c05e2 - Merge pull request timvideos#240 from danielkucera/patch-1 <enjoy-digital> |\ \ | |/ |/| | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera> |/ * 2b815f70 - Merge pull request timvideos#235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital> |\ | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo> |/ * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec> * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec> * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec> * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec> * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec> * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec> * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec> * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec> * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec> * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec> * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec> * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec> * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec> * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec> * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec> * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec> * 236070fd - cores: -x on spi.py <Florent Kermarrec> * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec> * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec> * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec> * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec> * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec> * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec> * ae00482d - Merge pull request timvideos#223 from sergachev/master <enjoy-digital> * fdb119cb - support vivado incremental implementation <Ilia Sergachev> * litex-renode changed from b3fdb9b to 742360f * 742360f - Merge pull request timvideos#15 from antmicro/zephyr_dts <Tim Ansell> |\ | * c9b9651 - Add script generating DTS overlay for Zephyr <Mateusz Holenko> * | b0ebee5 - Merge pull request timvideos#14 from antmicro/memory_regions_verification <Mateusz Hołenko> |/ * ad52a03 - Verify memory sub-regions <Mateusz Holenko> * 2cb6886 - Rework handling address/size values in `Configuration` <Mateusz Holenko> * 462df23 - Simplify flash memory generation <Mateusz Holenko> * 3a1f7c8 - Generate memory regions size in hex <Mateusz Holenko> * f010339 - Print peripheral address in hex <Mateusz Holenko> * 0742996 - Fix a typo <Mateusz Holenko> * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq> * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq> * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq> * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq> * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq> * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq> * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq> * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq> * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq> * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq> * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq> * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq> * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz> * f4fcd10 - fix previous commit <Sebastien Bourdeauducq> * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq> Full submodule status -- 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD) 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD) 401554f94c5fbfae1a4de98504c5c2994a6f714a litedram (remotes/origin/HEAD) 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD) 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (remotes/origin/HEAD) 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD) 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD) a54b80b9b4eaa6defca99b0749da8426535bbb62 litex (v0.1-1333-ga54b80b9) 742360f2ba4c400c6164908f03c6ca3d965f168b litex-renode (remotes/origin/HEAD) 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)

ewenmcneill · 2020-03-13T09:05:35Z

About the only thing I can think of to do is to try setting per target defaults via the target Makefile, and then do something like what is done with the CPU:

Setting the defaults via the Makefile seems to be the right approach. And we can actually inject them via the command line (which actually happens with the CPU anyway; not sure why it's being set again from the environment...).

I've got a working, relatively cleaned up, example with the latest litex at:

https://github.com/ewenmcneill/litex-buildenv/tree/refactor-tinyfpga-bx

but it's only been fixed up for the TinyFPGA BX.

However I do get a working BIOS boot, with 10kB of RAM. (I did briefly try to get Quad SPI working, but naively swapping from Single SPI to Quad SPI didn't both, so I gave up on that.)

Ewen

PS: There's still no firmware, just "none", so it doesn't boot anything after the BIOS. But I think if I had a firmware it'd work. (I did spend a while trying to get the default litex-buildenv firmware (ie, not the stub) to build for the TinyFPGA, without success; it keeps building the stub firmware, and then being surprised that it can't find software/firmware/firmware.bin. And MicroPython needs some CSR function porting...

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar 13 2020 21:38:53
 BIOS CRC passed (a7851729)

 Migen git sha1: d11565a
 LiteX git sha1: b5bddc23

--=============== SoC ==================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      10KB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Executing booted program at 0x20058008

--============= Liftoff! ===============--

GitHub
ewenmcneill/litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - ewenmcneill/litex-buildenv

ewenmcneill · 2020-03-14T07:57:05Z

(I wrote most of this last night, but reaiised today that I hadn't actually added it to the ticket.)

\o/

I got MicroPython to boot. It needed one more tweak to link in the litex hw include directory, for the new CSR routines; plus moving third_party/ports/fupy/hw out of the way (which was a cached copy of those litex routines -- an old cached copy).

So after a lot of work, I'm now back where I was: able to build/run MicroPython on the TinyFPGA BX via litex-buildenv.

The WIP versions of changes I'm using are https://github.com/ewenmcneill/litex-buildenv/tree/refactor-tinyfpga-bx and https://github.com/ewenmcneill/fupy-micropython/tree/modern-litex (the latter of which has just one change). And since with a new enough litex all the unusual/small memory size issues and XIP issues are resolved, I've closed the litex issued I opened (ie, enjoy-digital/litex#417).

I suspect the next step is to work on #366 (ie, updating the litex dependency), which will probably require some manual porting/updates, so that it's at a new enough version that these unusual RAM size/XIP platforms work again. (It turns out there is an auto dependency updater for litex too, but it's not able to get a successful build so it's not updating litex. Ports like my refractor-tinyfpga-bx branch are possibly required to get good builds, since the main change is that the litex default ROM/SRAM is no longer zero.)

Ewen

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Mar 13 2020 22:35:21
 BIOS CRC passed (57d4b565)

 Migen git sha1: d11565a
 LiteX git sha1: b5bddc23

--=============== SoC ==================--
CPU:       LM32 @ 16MHz
ROM:       32KB
SRAM:      10KB

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from flash...
Executing booted program at 0x20058008

--============= Liftoff! ===============--
MicroPython v1.9.4-1430-ge23216bf2 on 2020-03-13; litex with lm32
>>> print("Hello World")
Hello World
>>>

GitHub
ewenmcneill/litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! - ewenmcneill/litex-buildenv

GitHub
ewenmcneill/fupy-micropython
MicroPython port to litex FPGA platforms. Contribute to ewenmcneill/fupy-micropython development by creating an account on GitHub.

ewenmcneill · 2020-04-07T21:45:26Z

@niklasnisbeth Now that #348 is merged, which updates to a litex which has working non-power-of-2 memory and a working set of compile flags, I think the iCE40 HX8K EVB is likely to work again (and if it doesn't, it'll hopefully just need some minor tweaks as made to the other platforms).

Can you test again when you get a chance and let us know? (TinyFPGA BX is working again for me; that was tested before we merged #348.)

Ewen

niklasnisbeth · 2020-05-05T21:59:59Z

Hello. It has taken me a while to get litex-buildenv to work again, but tonight I have been able to try from rev. a3d3477.

Using TARGET=ice40_hx8k_b_evn and FIRMWARE=stub, neither CPU=lm32.minimal nor CPU=vexriscv.minimal produce any output on /dev/ttyUSB1 at 115200 baud. I do get a very slow binary counter on the LEDs, but I'm not sure where that's coming from. Anything else in FIRMWARE does not allow me to build an image - I thought micropython was supposed to work there?

ewenmcneill · 2020-05-06T05:03:55Z

Thanks for testing. lm32.minimal is basically what I was testing with on a TinyFPGA BX, so that's the most likely to work (I suspect vexriscv.minimal should work too, but I don't know when anyone last tested that on an iCE40 from litex-buildenv).

MicroPython should build now (at least it did a couple of weeks ago), but it needs to be built with a custom script, eg:

...
export FIRMWARE=micropython
make gateware
scripts/build-micropython.sh

(It'd be nice if FIRMWARE=micropython and "make image" or similar was sufficient, but that hasn't been set up in the Makefiles AFAIK.)

Assuming the image built and flashed okay, my guess is that the "slow binary counter on the LEDs" is something that's built into the gateware (ie, not reliant on the CPU), and maybe the CPU still isn't booting correctly.

Unfortunately I don't have a ice40_hx8k_b_evn to test myself. But my guess would be that maybe something's still needing to be converted in the target file to ensure that the CPU/RAM gets built with the correct memory layout.

Ewen

mithro mentioned this issue Jan 8, 2020

TinyFPGA BX: BIOS/Micropython does not start #282

Closed

mithro mentioned this issue Jan 29, 2020

Problem with make firmware-connect #304

Open

ewenmcneill mentioned this issue Mar 8, 2020

Regression: small sram, non power of 2 RAM size, firmware XIP (iCE40 8K: TinyFPGA BX/HX8K) enjoy-digital/litex#417

Closed

ewenmcneill mentioned this issue Mar 8, 2020

Update litex submodule (currently 2019-11-18) #366

Closed

mithro mentioned this issue Mar 26, 2020

Update submodules and modernize platforms/target files #348

Merged

ewenmcneill mentioned this issue Apr 4, 2020

Permit target RAM size override to smaller size #381

Closed

ewenmcneill mentioned this issue Apr 7, 2020

Cleanup (and fix) the ice40_hx8k_b_env target #384

Open

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Ice40 HX8K EVB issues #277

Ice40 HX8K EVB issues #277

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Ice40 HX8K EVB issues #277

Ice40 HX8K EVB issues #277

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