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Fix endianness #176

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merged 2 commits into from
Jul 25, 2019
+11 −6
Merged

Fix endianness #176

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f21f4f2
targets: set proper ethmac endianness
mateusz-holenko Jul 24, 2019
2836f89
firmware: set proper endianness in uip
mateusz-holenko Jul 24, 2019
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5 changes: 5 additions & 0 deletions firmware/uip/contiki-conf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,12 @@ typedef unsigned int uip_stats_t;
#endif

/* uIP configuration */
#if defined(__lm32__) || defined(__or1k__)
#define UIP_CONF_BYTE_ORDER UIP_BIG_ENDIAN
#else
#define UIP_CONF_BYTE_ORDER UIP_LITTLE_ENDIAN
#endif

#define UIP_CONF_LLH_LEN 14
#define UIP_CONF_BROADCAST 1
#define UIP_CONF_LOGGING 1
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2 changes: 1 addition & 1 deletion targets/arty/net.py
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Expand Up @@ -31,7 +31,7 @@ def __init__(self, platform, *args, **kwargs):
platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(
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I don't quite understand why LiteEthMAC needs to understand the cpu endianness? However it looks like that is something from upstream, not something you invented?

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The MAC converts 32-bit writes/reads to/from 8-bit streams so needs to know the endiannness to know in which order reading/storing the streams.

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I have detected the problems when testing the firmware on HW. Without setting the proper endianess, data read from liteeth buffers had each 4-byte chunk reverted, causing the software to fail to detect the proper type of packet and drop it in a process.

After realising what was going on, I tested the pure LiteX platform and it worked fine. Diffing them pointed to the endianness property (not set in LiteX-BuildEnv).

phy=self.ethphy, dw=32, interface="wishbone")
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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2 changes: 1 addition & 1 deletion targets/atlys/net.py
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Expand Up @@ -32,7 +32,7 @@ def __init__(self, platform, *args, **kwargs):
self.clk_freq)

self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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2 changes: 1 addition & 1 deletion targets/mimas_a7/net.py
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Expand Up @@ -27,7 +27,7 @@ def __init__(self, platform, *args, **kwargs):
platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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2 changes: 1 addition & 1 deletion targets/nexys_video/net.py
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ def __init__(self, platform, *args, **kwargs):
platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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2 changes: 1 addition & 1 deletion targets/opsis/net.py
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Expand Up @@ -33,7 +33,7 @@ def __init__(self, platform, *args, **kwargs):
platform.request("eth"))
self.platform.add_source("gateware/rgmii_if.vhd")
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy, dw=32, interface="wishbone")
phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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2 changes: 1 addition & 1 deletion targets/sim/net.py
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)

self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)

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