init globals and bss in start.S

examples/picosoc/README.md

@@ -0,0 +1,74 @@
+# Video Notes
+
+Git repository https://github.com/mattvenn/TinyFPGA-BX/tree/master/examples/picosoc
+
+The README.md contains information on:
+
+* Information about installing the toolchains
+* Electrical wiring for the demos 
+* Precompiled firmware binaries:
+	* master - starting point
+	* ws2812 - includes ws2812 driver and serial driver
+
+# PicoSOC TinyFPGA example
+
+PicoSOC is an SOC - system on chip. It includes everything you need to 
+run a RiscV CPU on the TinyFPGA.
+
+The RiscV CPU is PicoRV32, made by Clifford Wolf. The original repo is here:
+
+https://github.com/cliffordwolf/picorv32
+
+The SOC example that uses the PicoRV32 was originally made for the Lattice 8k evaluation
+board. This example has been modified to work with the TinyFPGA by Luke from TinyFPGA.
+
+# FPGA Toolchain
+
+You can synthesise the demo with the [icestorm](http://www.clifford.at/icestorm/) toolchain.
+A very convient way to install the toolchain is to use [APIO](https://github.com/FPGAwars/apio)
+And then set your path to include the installed tools and copy the chipdb and yosys files:
+
+	export PATH=$PATH:~/.apio/packages/toolchain-icestorm/bin/
+	sudo cp -r ~/.apio/packages/toolchain-icestorm/share/icebox/ /usr/local/share/
+	sudo cp -r ~/.apio/packages/toolchain-icestorm/share/yosys /usr/local/share/
+
+
+You will also need tinyprog:
+
+	pip install tinyprog
+
+For more info on the TinyFPGA tools and setup see the TinyFPGA page: https://tinyfpga.com/bx/guide.html
+
+At this point you should be able to run make upload to synthesise the hardware and program to the TinyFPGA.
+I have precompiled the firmware.c and added the firmware.bin and hex files to the repo so you don't need GCC.
+
+If you just want to see the demos in the video, you can switch to the ws2812 branch
+
+	git checkout ws2812
+
+Which should allow you to program the precompiled firmware or run the simulation without installing GCC.
+
+# GCC for firmware compilation
+
+As this is a RiscV CPU running on the FPGA, we really need the RiscV GCC tools to get the most out of it!
+Fetching the repos and compiling took about 3 hours on my 4 year old T400 Lenovo laptop. Full instructions
+here: https://github.com/cliffordwolf/picorv32#building-a-pure-rv32i-toolchain
+
+What I did was:
+
+	sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+		libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+		gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+	git clone git@github.com:cliffordwolf/picorv32.git
+	cd picorv32/
+	time make -j2 build-riscv32i-tools
+	export PATH=$PATH:/opt/riscv32i/bin/
+
+Then make firmware.bin should work and you can then write your own c program or edit my demos.
+
+# Wiring for the demo
+
+* Serial TX is pin 1
+* Serial RX is pin 2
+* WS2812 data is pin 3

examples/picosoc/firmware.c

@@ -25,11 +25,6 @@ uint32_t set_irq_mask(uint32_t mask); asm (
 void main() {
     set_irq_mask(0xff);
 
-    // zero out .bss section
-    for (uint32_t *dest = &_sbss; dest < &_ebss;) {
-        *dest++ = 0;
-    }
-
     // switch to dual IO mode
     reg_spictrl = (reg_spictrl & ~0x007F0000) | 0x00400000;
 

examples/picosoc/start.S

@@ -209,10 +209,36 @@ start:
 	addi x30, zero, 0
 	addi x31, zero, 0
 
+    # copy data section
+    la a0, _sidata                      # load _sidata to a0
+    la a1, _sdata                       # load _sdata to a1
+    la a2, _edata                       # load _edata to a2
+    bge a1, a2, end_init_data           # if _edata > _sdata jump to end
+
+loop_init_data:
+    lw a3, 0(a0)                        # load data at a0 to a3
+    sw a3, 0(a1)                        # store data in a3 to a1 (_sdata)
+    addi a0, a0, 4                      # add 4 to a0
+    addi a1, a1, 4                      # add 4 to a1
+    blt a1, a2, loop_init_data          # if a1 < a2 finish
+
+end_init_data:
+
+    # zero-init bss section
+    la a0, _sbss
+    la a1, _ebss
+    bge a0, a1, end_init_bss
+
+loop_init_bss:
+    sw zero, 0(a0)
+    addi a0, a0, 4
+    blt a0, a1, loop_init_bss
+
+end_init_bss:
+    call main
 
-        call main
 loop:
-        j loop
+    j loop