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[arm64] Factor out unimplemented errors
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titzer committed Feb 7, 2024
1 parent c67128b commit 649ecea
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Showing 7 changed files with 39 additions and 39 deletions.
35 changes: 13 additions & 22 deletions aeneas/src/arm64/Arm64Backend.v3
Original file line number Diff line number Diff line change
Expand Up @@ -18,24 +18,21 @@ class Arm64Target extends Target {
def configureCompiler(compiler: Compiler) {}

def configureProgram(prog: Program) {
prog.ERROR.fail("not implemented");
prog.ERROR.unimplemented();
}

def computeFieldOffsets(prog: Program, b: Vector<IrField>, start: int) {
prog.ERROR.fail("not implemented");
prog.ERROR.unimplemented();
}
def addRoots(compiler: Compiler, prog: Program) {
prog.ERROR.fail("not implemented");
prog.ERROR.unimplemented();
}

def emit(compiler: Compiler, prog: Program) {
prog.ERROR.fail("not implemented");
prog.ERROR.unimplemented();
}
}

// TODO: negative object headers
class Arm64Backend extends MachBackend {
var asm: Arm64MacroAssembler; // TODO
var asm: Arm64MacroAssembler;
def test: bool;
var codegen: SsaArm64Gen;
var allocateRegs: void -> void;
Expand All @@ -54,7 +51,7 @@ class Arm64Backend extends MachBackend {
asm = Arm64MacroAssembler.new();
if (ri_gc != null) {
// call the RiRuntime.gc() method
mach.fail("not implemented");
prog.ERROR.unimplemented();
} else {
// there is no appropriate RiRuntime.gc() method
objReg = Arm64Regs.R0;
Expand All @@ -67,34 +64,28 @@ class Arm64Backend extends MachBackend {
}

// Override MachBackend

def genEntryStub() {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

def genAllocStub() {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

def genCodeFromSsa() {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

def patchCodeAddr(w: DataWriter, a: Addr, posAddr: int) {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

def genSignalHandlerStub() {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

def genFatalStub(ex: string, addr: Addr) {
mach.fail("not implemented");
prog.ERROR.unimplemented();
}

// Methods overridden for each OS target
def genSigHandlerInstall(signo: int, handler: Addr);
def asm_exit_r(r: X86_64Gpr);
def asm_exit_code(code: int);
def genTestOutput(main: IrMethod, frame: MachFrame);
}
}
7 changes: 5 additions & 2 deletions aeneas/src/arm64/Arm64MacroAssembler.v3
Original file line number Diff line number Diff line change
@@ -1,5 +1,8 @@
// Copyright 2024 Virgil Authors. All rights reserved.
// See LICENSE for details of Apache 2.0 license.

// TODO
class Arm64MacroAssembler extends Arm64Assembler {}
// An extended Arm64Assembler that has additional machine-level utilities, such as
// recording patch locations and translating between regset locations and arm64
// registers/memory.
class Arm64MacroAssembler extends Arm64Assembler {
}
26 changes: 13 additions & 13 deletions aeneas/src/arm64/SsaArm64Gen.v3
Original file line number Diff line number Diff line change
Expand Up @@ -6,35 +6,35 @@ def Conds: Arm64Conds; // TODO

// Code generation for the Arm64 backend
class SsaArm64Gen extends SsaMachGen {
def asm: Arm64MacroAssembler; // TODO
def asm: Arm64MacroAssembler;
def m = SsaInstrMatcher.new();
def dwarf: Dwarf; // What is this?
def dwarf: Dwarf;

new(context: SsaContext, mach: MachProgram, asm, w: MachDataWriter, dwarf)
super(context, mach, Arm64RegSet.SET, w) {}

// Overidden Architecture Specific Routines
def visitApply(block: SsaBlock, i: SsaApplyOp) {
match (i.op.opcode) {
_ => context.fail("not implemented"); // TODO
_ => context.unimplemented(); // TODO
}
}

def visitThrow(block: SsaBlock, i: SsaThrow) { context.fail("not implemented"); }
def visitIf(block: SsaBlock, i: SsaIf) { context.fail("not implemented"); }
def visitSwitch(block: SsaBlock, i: SsaSwitch) { context.fail("not implemented"); }
def visitGoto(block: SsaBlock, target: SsaGoto) { context.fail("not implemented"); }
def visitThrow(block: SsaBlock, i: SsaThrow) { context.unimplemented(); }
def visitIf(block: SsaBlock, i: SsaIf) { context.unimplemented(); }
def visitSwitch(block: SsaBlock, i: SsaSwitch) { context.unimplemented(); }
def visitGoto(block: SsaBlock, target: SsaGoto) { context.unimplemented(); }

// Override Code Generation
def assemble(opcode: int, x: Array<Operand>) {
context.fail("not implemented");
context.unimplemented();
}

// Regalloc callbacks to add moves
def genSaveLocal(reg: int, v: VReg) { context.fail("not implemented"); }
def genRestoreLocal(v: VReg, reg: int) { context.fail("not implemented"); }
def genMoveLocLoc(src: (VReg, int), dst: (VReg, int), regClass: RegClass) { context.fail("not implemented"); }
def genSaveLocal(reg: int, v: VReg) { context.unimplemented(); }
def genRestoreLocal(v: VReg, reg: int) { context.unimplemented(); }
def genMoveLocLoc(src: (VReg, int), dst: (VReg, int), regClass: RegClass) { context.unimplemented(); }

// Register allocation callback to prepend a move
def genMoveValLoc(src: VReg, dst: (VReg, int), regClass: RegClass) { context.fail("not implemented"); }
}
def genMoveValLoc(src: VReg, dst: (VReg, int), regClass: RegClass) { context.unimplemented(); }
}
2 changes: 1 addition & 1 deletion aeneas/src/mach/MachProgram.v3
Original file line number Diff line number Diff line change
Expand Up @@ -333,7 +333,7 @@ class MachProgram extends TargetProgram {
if (region.space.bigEndian) w.put_b64be(a.get<long>());
else w.put_b64(a.get<long>());
}
else return prog.ERROR.fail("unexpected data item in region");
else return fail("unexpected data item in region");
}
def encodeField(w: DataWriter, f: IrField) {
// encode a component's field at the address
Expand Down
3 changes: 3 additions & 0 deletions aeneas/src/main/Error.v3
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,9 @@ class ErrorGen(maxErrors: int) {
if (errorType != null) return errorType;
return errorType = getErrorTypeCon("?").create0();
}
def unimplemented() {
fail("not implemented");
}
def fail(msg: string) {
if (CLOptions.FATAL.get()) return V3.fail(msg);
addError(null, null, V3Exception.InternalError, msg);
Expand Down
2 changes: 1 addition & 1 deletion aeneas/src/main/Version.v3
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,6 @@

// Updated by VCS scripts. DO NOT EDIT.
component Version {
def version: string = "III-7.1685";
def version: string = "III-7.1686";
var buildData: string;
}
3 changes: 3 additions & 0 deletions aeneas/src/ssa/SsaContext.v3
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,9 @@ class SsaContext(compiler: Compiler, prog: Program) {
graph = if(m != null, m.ssa);
block = if(graph != null, graph.startBlock);
}
def unimplemented() {
fail("not implemented");
}
def fail(msg: string) {
// XXX: render SSA of failing method/block by default?
prog.ERROR.fail(where().puts(msg).toString());
Expand Down

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