Disable splitting of spills in GlobalRegAlloc (#323)

aeneas/src/mach/GlobalRegAlloc.v3

@@ -4,6 +4,7 @@
 def verbose = false;
 def colorVerbose = false;
 def COALESCE = false;
+def SPLIT_SPILLS = false; // TODO: fix splitting of spills
 
 // Implements global register allocation via graph coloring, including spilling, splitting,
 // and coalescing.
@@ -617,7 +618,7 @@ class GlobalRegAlloc(regSet: MachRegSet, codegen: SsaMachGen) {
 	// Decide whether to insert reload right before this use or on block level.
 	def processSpill(vreg: VReg, constraint: int, block: SsaBlock) {
 		var node = graph.nodes[vreg.varNum];
-		if (node.defBlock == block) {
+		if (!SPLIT_SPILLS || node.defBlock == block) {
 			var newVreg = codegen.dupVReg(vreg);
 			newVreg.notSpillable = true;
 			newVreg.reloadFrom = vreg;
@@ -669,6 +670,7 @@ class GlobalRegAlloc(regSet: MachRegSet, codegen: SsaMachGen) {
 	// Insert reload at the start of the commonDominator block
 	def insertReload(vreg: VReg, node: Node) {
 		node.commonDominator = findDominatorOutOfLoop(node);
+		// TODO(fix): this can sometimes insert the reload before the definition.
 		codegen.insertReload(vreg, (node.newVreg, 0), codegen.instrs[node.commonDominator.mark].next);
 		blockReloads[node.commonDominator.mark].put(node.newVreg);
 	}