KGPE-D16 boards: Adding VBOOT+measured boot, musl-cross patch and 4.1…

…1 patch brought up per linuxboot#709
tlaurion · Sep 19, 2020 · d04914c · d04914c
1 parent 4306f00
commit d04914c
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diff --git a/config/coreboot-kgpe-d16_server-whiptail.config b/config/coreboot-kgpe-d16_server-whiptail.config
@@ -5,10 +5,13 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_VENDOR_ASUS=y
 CONFIG_UART_FOR_CONSOLE=1
 CONFIG_BOARD_ASUS_KGPE_D16=y
+CONFIG_VBOOT=y
 CONFIG_DRIVERS_PS2_KEYBOARD=y
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
 CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_VBOOT_MEASURED_BOOT=y
+CONFIG_USER_TPM1=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
 CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="../../build/kgpe-d16_server-whiptail/bzImage"

diff --git a/config/coreboot-kgpe-d16_server.config b/config/coreboot-kgpe-d16_server.config
@@ -5,10 +5,13 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_VENDOR_ASUS=y
 CONFIG_UART_FOR_CONSOLE=1
 CONFIG_BOARD_ASUS_KGPE_D16=y
+CONFIG_VBOOT=y
 CONFIG_DRIVERS_PS2_KEYBOARD=y
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
 CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_VBOOT_MEASURED_BOOT=y
+CONFIG_USER_TPM1=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
 CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="../../build/kgpe-d16_server/bzImage"

diff --git a/config/coreboot-kgpe-d16_workstation-usb_keyboard.config b/config/coreboot-kgpe-d16_workstation-usb_keyboard.config
@@ -5,10 +5,13 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_VENDOR_ASUS=y
 CONFIG_UART_FOR_CONSOLE=1
 CONFIG_BOARD_ASUS_KGPE_D16=y
+CONFIG_VBOOT=y
 CONFIG_DRIVERS_PS2_KEYBOARD=y
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
 CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_VBOOT_MEASURED_BOOT=y
+CONFIG_USER_TPM1=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
 CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="../../build/kgpe-d16_workstation-usb_keyboard/bzImage"

diff --git a/config/coreboot-kgpe-d16_workstation.config b/config/coreboot-kgpe-d16_workstation.config
@@ -5,10 +5,13 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_VENDOR_ASUS=y
 CONFIG_UART_FOR_CONSOLE=1
 CONFIG_BOARD_ASUS_KGPE_D16=y
+CONFIG_VBOOT=y
 CONFIG_DRIVERS_PS2_KEYBOARD=y
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
 CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_VBOOT_MEASURED_BOOT=y
+CONFIG_USER_TPM1=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
 CONFIG_PAYLOAD_LINUX=y
 CONFIG_PAYLOAD_FILE="../../build/kgpe-d16_workstation/bzImage"

diff --git a/patches/coreboot-4.11/0001-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch b/patches/coreboot-4.11/0001-cpu-x86-smm-Use-PRIxPTR-to-print-uintptr_t.patch
@@ -0,0 +1,47 @@
+From 06f2fcc0ffc1a903f304d8a3382f3a57163989a1 Mon Sep 17 00:00:00 2001
+From: Jacob Garber <jgarber1@ualberta.ca>
+Date: Mon, 4 Nov 2019 09:35:15 -0700
+Subject: [PATCH] cpu/x86/smm: Use PRIxPTR to print uintptr_t
+
+Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This
+fixes a compilation error when targeting x86_64 or using Clang 9.0.0.
+
+Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f
+Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
+---
+ src/cpu/x86/smm/tseg_region.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c
+index a8b8bb7b9a..5b5c5729d5 100644
+--- a/src/cpu/x86/smm/tseg_region.c
++++ b/src/cpu/x86/smm/tseg_region.c
+@@ -17,6 +17,7 @@
+ #include <cpu/x86/smm.h>
+ #include <stage_cache.h>
+ #include <types.h>
++#include <inttypes.h>
+
+ /*
+  *        Subregions within SMM
+@@ -88,11 +89,11 @@ void smm_list_regions(void)
+ 		return;
+
+ 	printk(BIOS_DEBUG, "SMM Memory Map\n");
+-	printk(BIOS_DEBUG, "SMRAM       : 0x%zx 0x%zx\n", base, size);
++	printk(BIOS_DEBUG, "SMRAM       : 0x%" PRIxPTR " 0x%zx\n", base, size);
+
+ 	for (i = 0; i < SMM_SUBREGION_NUM; i++) {
+ 		if (smm_subregion(i, &base, &size))
+ 			continue;
+-		printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
++		printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size);
+ 	}
+ }
+-- 
+2.21.1
+
+
diff --git a/patches/coreboot-4.11/0010-cross-compiler-support.patch b/patches/coreboot-4.11/0010-cross-compiler-support.patch
@@ -0,0 +1,27 @@
+--- clean/coreboot-4.8.1/Makefile	2018-05-16 21:00:17.000000000 +0200
++++ coreboot-4.8.1/Makefile	2020-01-08 17:01:32.998287979 +0100
+@@ -152,6 +152,24 @@
+
+ -include .xcompile
+
++ifneq "$(CROSS)" ""
++  $(info coreboot: Using $(CROSS)gcc)
++  CROSS_COMPILE_x86_32	:= $(CROSS)
++  CC_x86_32		:= $(CROSS_COMPILE_x86_32)gcc
++  CPP_x86_32		:= $(CROSS_COMPILE_x86_32)cpp
++  AS_x86_32		:= $(CROSS_COMPILE_x86_32)as --32
++  LD_x86_32		:= $(CROSS_COMPILE_x86_32)ld.bfd -b elf32-i386 -melf_i386
++  NM_x86_32		:= $(CROSS_COMPILE_x86_32)nm
++  OBJCOPY_x86_32	:= $(CROSS_COMPILE_x86_32)objcopy
++  OBJDUMP_x86_32	:= $(CROSS_COMPILE_x86_32)objdump
++  READELF_x86_32	:= $(CROSS_COMPILE_x86_32)readelf
++  STRIP_x86_32		:= $(CROSS_COMPILE_x86_32)strip
++  AR_x86_32		:= $(CROSS_COMPILE_x86_32)ar
++  GNATBIND_x86_32	:= $(CROSS_COMPILE_x86_32)gnatbind
++  COMPILER_RT_x86_32	:= $(shell $(CC_x86_32) --print-libgcc-file-name)
++endif
++
++
+ ifneq ($(XCOMPILE_COMPLETE),1)
+ $(shell rm -f .xcompile)
+ $(error .xcompile deleted because it's invalid. \