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Support low bit weights in nnvm (apache#2)
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/*! | ||
* Copyright (c) 2017 by Contributors | ||
* \file lowbit.cc | ||
* \brief Support operators for lowbit | ||
*/ | ||
#include <tvm/tvm.h> | ||
#include <tvm/expr.h> | ||
#include <tvm/packed_func_ext.h> | ||
#include <nnvm/op.h> | ||
#include <nnvm/node.h> | ||
#include <nnvm/layout.h> | ||
#include <nnvm/op_attr_types.h> | ||
#include <nnvm/compiler/op_attr_types.h> | ||
#include <nnvm/top/nn.h> | ||
#include "./nn_common.h" | ||
#include "../op_common.h" | ||
#include "../elemwise_op_common.h" | ||
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namespace nnvm { | ||
namespace top { | ||
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struct BitPackParam : public dmlc::Parameter<BitPackParam> { | ||
int lanes; | ||
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DMLC_DECLARE_PARAMETER(BitPackParam) { | ||
DMLC_DECLARE_FIELD(lanes).set_lower_bound(1) | ||
.describe("Number of lanes packed in one element"); | ||
} | ||
}; | ||
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// dense | ||
DMLC_REGISTER_PARAMETER(BitPackParam); | ||
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inline bool BitPackInferShape(const nnvm::NodeAttrs& attrs, | ||
std::vector<TShape>* in_shape, | ||
std::vector<TShape>* out_shape) { | ||
const BitPackParam& param = nnvm::get<BitPackParam>(attrs.parsed); | ||
CHECK_EQ(out_shape->size(), 1U); | ||
if ((*in_shape)[DenseParam::kData].ndim() != 0) { | ||
TShape dshape = (*in_shape)[0]; | ||
CHECK_EQ(dshape[dshape.ndim() - 1] % param.lanes, 0); | ||
dshape[dshape.ndim() - 1] /= param.lanes; | ||
NNVM_ASSIGN_OUTPUT_SHAPE(attrs, *out_shape, 0, dshape); | ||
return false; | ||
} | ||
return true; | ||
} | ||
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NNVM_REGISTER_OP(bitpack) | ||
.describe(R"code(Applies bit packing to innermost dimension. | ||
)code" NNVM_ADD_FILELINE) | ||
.add_argument("data", "nD Tensor", "Input data.") | ||
.add_argument("weight", "2D Tensor", "Weight matrix.") | ||
.add_argument("bias", "1D Tensor", "Bias parameter.") | ||
.add_arguments(BitPackParam::__FIELDS__()) | ||
.set_attr_parser(ParamParser<BitPackParam>) | ||
.set_attr<FGetAttrDict>("FGetAttrDict", ParamGetAttrDict<BitPackParam>) | ||
.set_num_outputs(1) | ||
.set_num_inputs(1) | ||
.set_support_level(5) | ||
.set_attr<FInferShape>("FInferShape", BitPackInferShape) | ||
.set_attr<FInferType>("FInferType", ElemwiseType<-1, 1>); | ||
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} // namespace top | ||
} // namespace nnvm |
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"""Bit packing operators""" | ||
from __future__ import absolute_import as _abs | ||
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import tvm | ||
from topi import util | ||
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from nnvm.top import registry as reg, OpPattern | ||
from nnvm.top import nn as _nn | ||
from nnvm.top.tensor import _fschedule_broadcast | ||
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def bitpack(data, bits, pack_type="int8", name="bitpack"): | ||
"""Packs lowest dimension into format needed by VTA | ||
Parameters | ||
---------- | ||
pack_axis : int | ||
index of the axis to pack in data | ||
bit_axis : int | ||
index of axis to place bit axis in resulting packed data | ||
Returns | ||
------- | ||
packed : Tensor | ||
The packed tensor. | ||
""" | ||
shape_vec = list(data.shape) | ||
if pack_type == 'int8': | ||
data_width = 8 | ||
elif pack_type == 'int16': | ||
data_width = 16 | ||
elif pack_type == 'int32': | ||
data_width = 32 | ||
else: | ||
raise RuntimeError("Unknown pack type %s" % pack_type) | ||
assert data_width % bits == 0 | ||
lanes = data_width // bits | ||
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# Data must be in multiples of the data_width | ||
assert util.get_const_int(shape_vec[-1]) % lanes == 0, "Not a multiple of word size" | ||
shape_vec[-1] = shape_vec[-1] // lanes | ||
oshape = tuple(shape_vec) | ||
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def _bitpack(*indices): | ||
ret = None | ||
mask = tvm.const((1 << bits) - 1, pack_type) | ||
for k in range(lanes): | ||
idx = list(indices) | ||
idx[-1] = idx[-1] * lanes + k | ||
elem = data(*idx).astype(pack_type) | ||
if k == 0: | ||
ret = elem & mask | ||
else: | ||
val = (elem & mask) << tvm.const(k * bits, pack_type) | ||
ret = ret | val | ||
return ret | ||
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return tvm.compute( | ||
oshape, _bitpack, name=name, tag='bitpack') | ||
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@reg.register_compute("bitpack", level=15) | ||
def compute_bitpack(attrs, inputs, out): | ||
lanes = attrs.get_int("lanes") | ||
dtype = inputs[0].dtype | ||
assert dtype == "int8" | ||
width = 8 | ||
assert width % lanes == 0 | ||
bits = 8 // lanes | ||
return bitpack(inputs[0], bits, dtype) | ||
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reg.register_schedule("bitpack", _fschedule_broadcast) | ||
reg.register_pattern("bitpack", OpPattern.INJECTIVE) |
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