OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Feb 23, 2025 - Verilog
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eda
Here are 41 public repositories matching this topic...
A High-performance Timing Analysis Tool for VLSI Systems
parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis
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May 26, 2023 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Feb 23, 2025 - Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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Oct 21, 2024 - Verilog
IceChips is a library of all common discrete logic devices in Verilog
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Nov 20, 2024 - Verilog
Tools for working with circuits as graphs in python
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Nov 17, 2023 - Verilog
A Standalone Structural Verilog Parser
flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc
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Mar 31, 2022 - Verilog
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex verilog yacc vlsi fan-out atpg electronic-design-automation fault-simulation sequential-circuits stuck-at combinational-circuits test-pattern vlsi-testing
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Nov 20, 2023 - Verilog
Plugins for Yosys developed as part of the F4PGA project.
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May 14, 2024 - Verilog
DATC RDF
routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree
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Jul 31, 2020 - Verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface
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May 28, 2023 - Verilog
7 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 1, 2022 - Verilog
9 track standard cells for GF180MCU provided by GlobalFoundries.
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Dec 5, 2022 - Verilog
"High density" digital standard cells for SKY130 provided by SkyWater.
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Feb 22, 2023 - Verilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design
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Dec 19, 2024 - Verilog
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