single-cycle-processor

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Here are 12 public repositories matching this topic...

martinKindall / risc-v-single-cycle

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A Single Cycle Risc-V 32 bit CPU

riscv systemverilog basys3 rv32i riscv32 basys3-fpga riscv-assembly single-cycle-processor

Updated Feb 11, 2023
SystemVerilog

martinKindall / mips_cpu

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Single Cycle 32 bit MIPS

fpga mips systemverilog basys3 mips-cpu single-cycle basys3-fpga single-cycle-processor

Updated Dec 24, 2022
SystemVerilog

Fahad-Habib / RISC-V-Single-Cycle-Processor

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Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

verilog systemverilog risc-v digital-system-design single-cycle-processor risc-v-architecture

Updated Apr 23, 2023
SystemVerilog

Elzawawy / mips-processor-simulator

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A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.

mips mips-architecture mips-simulator pipelined-processors single-cycle-processor multi-cycle-processor

Updated Aug 31, 2020
SystemVerilog

grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.

systemverilog risc-v riscv32 single-cycle-processor

Updated May 12, 2024
SystemVerilog

sts08015 / risc-v-lab

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Extended Version of COSE222 Lab

verilog systemverilog risc-v pipelined-processors single-cycle-processor

Updated Feb 12, 2023
SystemVerilog

Engineer-Ayesha-Shafique / RISC-V-Single-Cycle-Processor

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This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.

risc-v rv32i single-cycle-processor risc-v-single-cycle-processor

Updated Dec 24, 2023
SystemVerilog

kalhorghazal / Mips-SingleCycle

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Mips Single-Cycle, Computer Architecture course, University of Tehran

mips verilog-hdl mips-architecture mips-processor single-cycle-processor

Updated Feb 5, 2021
SystemVerilog

iamazizhaider / Single_Cycle_RiscV_Processor

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This project was designed to run on Nexys A7 Artix-7 FPGA Trainer Board. This processor written in System Verilog can run I-Type, R-Type, B-Type, S-Type RISC-V commands. The current instruction set that has been uploaded here finds the greatest common divisor of two numbers.

risc-v single-cycle-processor