[VTA][Chisel] End-to-end Inference with Chisel VTA (apache#4574)

* [VTA][Chisel] End-to-end Inference with Chisel VTA * Update TensorAlu.scala
tqchen · Dec 23, 2019 · 4e30e95 · 4e30e95
1 parent f99f4ef
commit 4e30e95
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/hardware/chisel/src/main/scala/core/TensorAlu.scala b/hardware/chisel/src/main/scala/core/TensorAlu.scala
@@ -230,7 +230,8 @@ class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
   tensorImm.data.valid := state === sReadTensorB
   tensorImm.data.bits.foreach { b =>
     b.foreach { c =>
-      c := dec.alu_imm
+      c := Mux(dec.alu_imm(C_ALU_IMM_BITS - 1),
+               Cat(-1.S((aluBits - C_ALU_IMM_BITS).W), dec.alu_imm), dec.alu_imm)
     }
   }