v0.5.0 release

Evolution summary:

core

new

• CI builder (windows and Linux)
• release artifacts
• spiOverJtag: altera version (virtual jtag)

update

• better list of boards and FPGA
• spiOverJtag: build system now based on edalize
• spiOverJtag: rewrite xilinx spiOverJtag vhd -> v
• spiOverJtag: use build.py for all devices, add xc6slx45
• epcq,spiFlash: epcq is now a subclass of spiFlash
• spiFlash: add verify and dump method

fix

• main: display error message if program fails
• configBitstreamParser: don't compute reverseByte, use a precomputed table: gain: 200ms for arty @30mhz
• progressBar: limit resolution

cable

update

• DFU: try to open dfu file VID/PID. If fails try with constructor VID/PID.

fix

• DFU: don't try to autodetect target to use
• ftdxxx: workaround for arty to program at 30MHz

parts

new

• Xilinx Spartan6 xc6slx100fgg484
• Gowin GW1N-2

update

• altera: use new epcq interface, add device type and prog type. Now more generic and not specific to cyc1000
• altera: add spi flash support for cyclone IV & cyclone V

boards

new

• Fomu support
• default clock speed in board configuration
• add VID/PID at board configuration level

update

• cyc1000: add fpga model and spi flash support
• Arty set default clock speed @ 10MHz
• de0nano: add fpga model and spi flash support
• qmTech: add fpga model and spi flash support
• pipistrello: add fpga mode and spi flash support

Contributors:

• Billy Stevens (@wasv):
• ultraembedded (@ultraembedded)
• Unai Martinez-Corral (@umarcor)