clmul: wip - reached name mangling error

- ./zig test ../test/behavior/carryless_mul.zig => error: undefined symbol: llvm.x86.pclmulqdq.v2i64

src/AstGen.zig

@@ -2177,6 +2177,7 @@ fn unusedResultExpr(gz: *GenZir, scope: *Scope, statement: Ast.Node.Index) Inner
             .reduce,
             .shuffle,
             .select,
+            .mul_carryless,
             .atomic_load,
             .atomic_rmw,
             .mul_add,
@@ -7537,7 +7538,7 @@ fn builtinCall(
             });
             return rvalue(gz, rl, result, node);
         },
-
+        
         .atomic_load => {
             const int_type = try typeExpr(gz, scope, params[0]);
             // TODO allow this pointer type to be volatile
@@ -7669,6 +7670,14 @@ fn builtinCall(
             });
             return rvalue(gz, rl, result, node);
         },
+        .mul_carryless => {
+            const result = try gz.addPlNode(.mul_carryless, node, Zir.Inst.MulCarryless{
+                .a = try expr(gz, scope, .none, params[0]),
+                .b = try expr(gz, scope, .none, params[1]),
+                .imm = try expr(gz, scope, .none, params[2]),
+            });
+            return rvalue(gz, rl, result, node);
+        },
         .async_call => {
             const result = try gz.addPlNode(.builtin_async_call, node, Zir.Inst.AsyncCall{
                 .frame_buffer = try expr(gz, scope, .none, params[0]),

src/BuiltinFn.zig

@@ -72,6 +72,7 @@ pub const Tag = enum {
     rem,
     return_address,
     select,
+    mul_carryless,
     set_align_stack,
     set_cold,
     set_eval_branch_quota,
@@ -634,6 +635,13 @@ pub const list = list: {
                 .param_count = 4,
             },
         },
+        .{
+            "@mulCarryless",
+            .{
+                .tag = .mul_carryless,
+                .param_count = 3,
+            },
+        },
         .{
             "@setAlignStack",
             .{

src/Sema.zig

@@ -333,6 +333,7 @@ pub fn analyzeBody(
             .reduce                       => try sema.zirReduce(block, inst),
             .shuffle                      => try sema.zirShuffle(block, inst),
             .select                       => try sema.zirSelect(block, inst),
+            .mul_carryless                => try sema.zirMulCarryless(block, inst),
             .atomic_load                  => try sema.zirAtomicLoad(block, inst),
             .atomic_rmw                   => try sema.zirAtomicRmw(block, inst),
             .mul_add                      => try sema.zirMulAdd(block, inst),
@@ -705,6 +706,7 @@ fn zirExtended(sema: *Sema, block: *Scope.Block, inst: Zir.Inst.Index) CompileEr
         .c_define           => return sema.zirCDefine(           block, extended),
         .wasm_memory_size   => return sema.zirWasmMemorySize(    block, extended),
         .wasm_memory_grow   => return sema.zirWasmMemoryGrow(    block, extended),
+        .mul_carryless      => @panic("TODO: zirExtended mulCarryless"),
         // zig fmt: on
     }
 }
@@ -8940,6 +8942,12 @@ fn zirSelect(sema: *Sema, block: *Scope.Block, inst: Zir.Inst.Index) CompileErro
     return sema.mod.fail(&block.base, src, "TODO: Sema.zirSelect", .{});
 }
 
+fn zirMulCarryless(sema: *Sema, block: *Scope.Block, inst: Zir.Inst.Index) CompileError!Air.Inst.Ref {
+    const inst_data = sema.code.instructions.items(.data)[inst].pl_node;
+    const src = inst_data.src();
+    return sema.mod.fail(&block.base, src, "TODO: Sema.zirMulCarryless", .{});
+}
+
 fn zirAtomicLoad(sema: *Sema, block: *Scope.Block, inst: Zir.Inst.Index) CompileError!Air.Inst.Ref {
     const inst_data = sema.code.instructions.items(.data)[inst].pl_node;
     const extra = sema.code.extraData(Zir.Inst.Bin, inst_data.payload_index).data;

src/Zir.zig

@@ -878,6 +878,9 @@ pub const Inst = struct {
         /// Implements the `@select` builtin.
         /// Uses the `pl_node` union field with payload `Select`.
         select,
+        /// Implements the `@mulCarryless` builtin.
+        /// Uses the `pl_node` union field with payload `MulCarryless`.
+        mul_carryless,
         /// Implements the `@atomicLoad` builtin.
         /// Uses the `pl_node` union field with payload `Bin`.
         atomic_load,
@@ -1189,6 +1192,7 @@ pub const Inst = struct {
                 .reduce,
                 .shuffle,
                 .select,
+                .mul_carryless,
                 .atomic_load,
                 .atomic_rmw,
                 .atomic_store,
@@ -1469,6 +1473,7 @@ pub const Inst = struct {
                 .reduce = .pl_node,
                 .shuffle = .pl_node,
                 .select = .pl_node,
+                .mul_carryless = .pl_node,
                 .atomic_load = .pl_node,
                 .atomic_rmw = .pl_node,
                 .atomic_store = .pl_node,
@@ -1604,6 +1609,10 @@ pub const Inst = struct {
         /// `operand` is payload index to `OverflowArithmetic`.
         /// `small` is unused.
         shl_with_overflow,
+        /// Implements the `@mulCarryless` builtin.
+        /// `operand` is payload index to `MulCarryless`.
+        /// `small` is unused.
+        mul_carryless,
         /// `operand` is payload index to `UnNode`.
         c_undef,
         /// `operand` is payload index to `UnNode`.
@@ -2858,6 +2867,12 @@ pub const Inst = struct {
         b: Ref,
     };
 
+    pub const MulCarryless = struct {
+        a: Ref,
+        b: Ref,
+        imm: Ref,
+    };
+
     pub const AsyncCall = struct {
         frame_buffer: Ref,
         result_ptr: Ref,

src/codegen/llvm/bindings.zig

@@ -452,6 +452,9 @@ pub const Builder = opaque {
     pub const buildUMulFixSat = ZigLLVMBuildUMulFixSat;
     extern fn ZigLLVMBuildUMulFixSat(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
 
+    pub const buildMulcl = ZigLLVMBuildMulcl;
+    extern fn ZigLLVMBuildMulcl(*const Builder, A: *const Value, B: *const Value, IMM: *const Value, Name: [*:0]const u8) *const Value;
+
     pub const buildUDiv = LLVMBuildUDiv;
     extern fn LLVMBuildUDiv(*const Builder, LHS: *const Value, RHS: *const Value, Name: [*:0]const u8) *const Value;
 

src/print_zir.zig

@@ -272,6 +272,7 @@ const Writer = struct {
             .union_init_ptr,
             .shuffle,
             .select,
+            .mul_carryless,
             .mul_add,
             .builtin_call,
             .field_parent_ptr,
@@ -495,6 +496,7 @@ const Writer = struct {
             .builtin_extern,
             .wasm_memory_size,
             .wasm_memory_grow,
+            .mul_carryless,
             => try stream.writeAll("TODO))"),
         }
     }

src/stage1/all_types.hpp

@@ -1776,6 +1776,7 @@ enum BuiltinFnId {
     BuiltinFnIdVectorType,
     BuiltinFnIdShuffle,
     BuiltinFnIdSelect,
+    BuiltinFnIdMulcl,
     BuiltinFnIdSplat,
     BuiltinFnIdSetCold,
     BuiltinFnIdSetRuntimeSafety,
@@ -2568,6 +2569,7 @@ enum Stage1ZirInstId : uint8_t {
     Stage1ZirInstIdVectorType,
     Stage1ZirInstIdShuffleVector,
     Stage1ZirInstIdSelect,
+    Stage1ZirInstIdMulcl,
     Stage1ZirInstIdSplat,
     Stage1ZirInstIdBoolNot,
     Stage1ZirInstIdMemset,
@@ -2689,6 +2691,7 @@ enum Stage1AirInstId : uint8_t {
     Stage1AirInstIdTruncate,
     Stage1AirInstIdShuffleVector,
     Stage1AirInstIdSelect,
+    Stage1AirInstIdMulcl,
     Stage1AirInstIdSplat,
     Stage1AirInstIdBoolNot,
     Stage1AirInstIdMemset,
@@ -4343,6 +4346,22 @@ struct Stage1AirInstSelect {
     Stage1AirInst *b;
 };
 
+struct Stage1ZirInstMulcl {
+    Stage1ZirInst base;
+
+    Stage1ZirInst *a;
+    Stage1ZirInst *b;
+    Stage1ZirInst *imm;
+};
+
+struct Stage1AirInstMulcl {
+    Stage1AirInst base;
+
+    Stage1AirInst *a;
+    Stage1AirInst *b;
+    Stage1AirInst *imm;
+};
+
 struct Stage1ZirInstSplat {
     Stage1ZirInst base;
 

src/stage1/astgen.cpp

@@ -198,6 +198,8 @@ void destroy_instruction_src(Stage1ZirInst *inst) {
             return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstShuffleVector *>(inst));
         case Stage1ZirInstIdSelect:
             return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSelect *>(inst));
+        case Stage1ZirInstIdMulcl:
+            return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstMulcl *>(inst));
         case Stage1ZirInstIdSplat:
             return heap::c_allocator.destroy(reinterpret_cast<Stage1ZirInstSplat *>(inst));
         case Stage1ZirInstIdBoolNot:
@@ -657,6 +659,10 @@ static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSelect *) {
     return Stage1ZirInstIdSelect;
 }
 
+static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstMulcl *) {
+    return Stage1ZirInstIdMulcl;
+}
+
 static constexpr Stage1ZirInstId ir_inst_id(Stage1ZirInstSplat *) {
     return Stage1ZirInstIdSplat;
 }
@@ -2059,6 +2065,21 @@ static Stage1ZirInst *ir_build_select(Stage1AstGen *ag, Scope *scope, AstNode *s
     return &instruction->base;
 }
 
+static Stage1ZirInst *ir_build_mul_carryless(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
+    Stage1ZirInst *a, Stage1ZirInst *b, Stage1ZirInst *imm)
+{
+    Stage1ZirInstMulcl *instruction = ir_build_instruction<Stage1ZirInstMulcl>(ag, scope, source_node);
+    instruction->a = a;
+    instruction->b = b;
+    instruction->imm = imm;
+
+    ir_ref_instruction(a, ag->current_basic_block);
+    ir_ref_instruction(b, ag->current_basic_block);
+    ir_ref_instruction(imm, ag->current_basic_block);
+
+    return &instruction->base;
+}
+
 static Stage1ZirInst *ir_build_splat_src(Stage1AstGen *ag, Scope *scope, AstNode *source_node,
     Stage1ZirInst *len, Stage1ZirInst *scalar)
 {
@@ -4689,6 +4710,30 @@ static Stage1ZirInst *astgen_builtin_fn_call(Stage1AstGen *ag, Scope *scope, Ast
                     arg0_value, arg1_value, arg2_value, arg3_value);
                 return ir_lval_wrap(ag, scope, select, lval, result_loc);
             }
+        case BuiltinFnIdMulcl:
+            {
+                // Used for the type expr
+                Scope *comptime_scope = create_comptime_scope(ag->codegen, node, scope);
+
+                AstNode *arg0_node = node->data.fn_call_expr.params.at(0);
+                Stage1ZirInst *arg0_value = astgen_node(ag, arg0_node, comptime_scope);
+                if (arg0_value == ag->codegen->invalid_inst_src)
+                    return arg0_value;
+
+                AstNode *arg1_node = node->data.fn_call_expr.params.at(1);
+                Stage1ZirInst *arg1_value = astgen_node(ag, arg1_node, scope);
+                if (arg1_value == ag->codegen->invalid_inst_src)
+                    return arg1_value;
+
+                AstNode *arg2_node = node->data.fn_call_expr.params.at(2);
+                Stage1ZirInst *arg2_value = astgen_node(ag, arg2_node, scope);
+                if (arg2_value == ag->codegen->invalid_inst_src)
+                    return arg2_value;
+
+                Stage1ZirInst *mulcl = ir_build_mul_carryless(ag, scope, node,
+                    arg0_value, arg1_value, arg2_value);
+                return ir_lval_wrap(ag, scope, mulcl, lval, result_loc);
+            }
         case BuiltinFnIdSplat:
             {
                 AstNode *arg0_node = node->data.fn_call_expr.params.at(0);

src/stage1/codegen.cpp

@@ -5303,6 +5303,13 @@ static LLVMValueRef ir_render_select(CodeGen *g, Stage1Air *executable, Stage1Ai
     return LLVMBuildSelect(g->builder, pred, a, b, "");
 }
 
+static LLVMValueRef ir_render_mulcl(CodeGen *g, Stage1Air *executable, Stage1AirInstMulcl *instruction) {
+    LLVMValueRef a = ir_llvm_value(g, instruction->a);
+    LLVMValueRef b = ir_llvm_value(g, instruction->b);
+    LLVMValueRef imm = ir_llvm_value(g, instruction->imm);
+    return ZigLLVMBuildMulcl(g->builder, a, b, imm, "");
+}
+
 static LLVMValueRef ir_render_splat(CodeGen *g, Stage1Air *executable, Stage1AirInstSplat *instruction) {
     ZigType *result_type = instruction->base.value->type;
     ir_assert(result_type->id == ZigTypeIdVector, &instruction->base);
@@ -7158,6 +7165,8 @@ static LLVMValueRef ir_render_instruction(CodeGen *g, Stage1Air *executable, Sta
             return ir_render_shuffle_vector(g, executable, (Stage1AirInstShuffleVector *) instruction);
         case Stage1AirInstIdSelect:
             return ir_render_select(g, executable, (Stage1AirInstSelect *) instruction);
+        case Stage1AirInstIdMulcl:
+            return ir_render_mulcl(g, executable, (Stage1AirInstMulcl *) instruction);
         case Stage1AirInstIdSplat:
             return ir_render_splat(g, executable, (Stage1AirInstSplat *) instruction);
         case Stage1AirInstIdVectorExtractElem:
@@ -9072,6 +9081,7 @@ static void define_builtin_fns(CodeGen *g) {
     create_builtin_fn(g, BuiltinFnIdVectorType, "Vector", 2);
     create_builtin_fn(g, BuiltinFnIdShuffle, "shuffle", 4);
     create_builtin_fn(g, BuiltinFnIdSelect, "select", 4);
+    create_builtin_fn(g, BuiltinFnIdMulcl, "mulCarryless", 3);
     create_builtin_fn(g, BuiltinFnIdSplat, "splat", 2);
     create_builtin_fn(g, BuiltinFnIdSetCold, "setCold", 1);
     create_builtin_fn(g, BuiltinFnIdSetRuntimeSafety, "setRuntimeSafety", 1);