pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenTitan: Open source silicon root of trust
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
RISC-V Debug Support for our PULP RISC-V Cores
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
A minimal GPU design in Verilog to learn how GPUs work from the ground up