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@Ralender Ralender commented Dec 2, 2020

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Thanks for fixing this!
Just a few nitpicks...

if (P.second->getTriple().isXilinxFPGA())
return false;

// Right off the bat, assume the presense of -foffload-static-lib means
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Suggested change
// Right off the bat, assume the presense of -foffload-static-lib means
// Right off the bat, assume the presence of -foffload-static-lib means

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@Ralender Ralender Dec 4, 2020

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This code is from intel so i don't think modifying it even a typo is good idea because it increases likelihood of conflicts.

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OK. I made intel/llvm#3079 for this

cl::sycl::range<1> NumOfWorkItems{Buffer.get_count()};
Queue.submit([&](cl::sycl::handler &cgh) {
sycl::accessor Accessor(Buffer, cgh, sycl::write_only);
cgh.single_task<class Test1>([=]() { Accessor[0] = 0; });
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cgh.single_task<class Test1>([=]() { Accessor[0] = 0; });
cgh.single_task<class Test1>([=] { Accessor[0] = 0; });

Queue.submit([&](cl::sycl::handler &cgh) {
sycl::accessor Accessor(Buffer, cgh, sycl::write_only);
cgh.single_task<class Test2>(
[=]() { Accessor[0] = 0; });
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[=]() { Accessor[0] = 0; });
[=] { Accessor[0] = 0; });

static_cast<const toolchains::XOCCToolChain &>(getToolChain());
InputInfoList SyclXoccArg = Inputs;

if (Inputs.size() > 1) {
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Add a comment explaining the high-level behaviour

@j-stephan j-stephan linked an issue Dec 4, 2020 that may be closed by this pull request
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keryell commented Jan 22, 2021

@Ralender what is the status of this PR?

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I think it should be good to merge. unless you have any objections

@keryell keryell merged commit b6f9427 into triSYCL:sycl/unified/next Feb 5, 2021
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sycl/build/bin/opt: error: expected top-level entity

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