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[TESTING] Add golden sample test for pipelining matmul with descriptors #5289

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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ void replaceUsesAndPropagateType(OpBuilder &builder, Operation *oldUse,
// Return the minClusterId and maxClusterId for the given ForOp.
std::pair<int, int> getMinMaxCluster(scf::ForOp &forOp);
std::pair<int, int> getStageCluster(Operation *op);
void setStageCluster(scf::ForOp &forOp, Operation *op, int stage, int cluster);
void setStageCluster(Operation *op, int stage, int cluster);
} // namespace triton
} // namespace mlir

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Original file line number Diff line number Diff line change
Expand Up @@ -64,11 +64,7 @@ class OpBuilderWithStage : public OpBuilder {
OpTy createWithStage(Location location, int stage, int cluster,
Args &&...args) {
OpTy op = OpBuilder::create<OpTy>(location, std::forward<Args>(args)...);
auto ctx = getContext();
op->setAttr(mlir::triton::kLoopStageAttrName,
IntegerAttr::get(IntegerType::get(ctx, 32), stage));
op->setAttr(mlir::triton::kLoopClusterAttrName,
IntegerAttr::get(IntegerType::get(ctx, 32), cluster));
tt::setStageCluster(op, stage, cluster);
return op;
}
using OpBuilder::create;
Expand Down Expand Up @@ -204,9 +200,8 @@ static int createAsyncCopy(scf::ForOp forOp, tt::LoadOp loadOp, Value alloc,
// Prefetch load if is not MMAV3 and is used by the dot.
if (loadToInfo[loadOp].usedByDot) {
assert(stageForFirstUse >= 1);
tt::setStageCluster(forOp, wait, stageForFirstUse - 1, maxClusterId + 1);
tt::setStageCluster(forOp, viewLoad, stageForFirstUse - 1,
maxClusterId + 1);
tt::setStageCluster(wait, stageForFirstUse - 1, maxClusterId + 1);
tt::setStageCluster(viewLoad, stageForFirstUse - 1, maxClusterId + 1);
retCode = stageForFirstUse - 1;
}
}
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Original file line number Diff line number Diff line change
Expand Up @@ -188,9 +188,8 @@ std::pair<int, int> mlir::triton::getStageCluster(Operation *op) {
return std::make_pair(stage, clusterId);
}

void mlir::triton::setStageCluster(scf::ForOp &forOp, Operation *op, int stage,
int cluster) {
auto ctx = forOp.getContext();
void mlir::triton::setStageCluster(Operation *op, int stage, int cluster) {
auto ctx = op->getContext();
op->setAttr(mlir::triton::kLoopStageAttrName,
IntegerAttr::get(IntegerType::get(ctx, 32), stage));
op->setAttr(mlir::triton::kLoopClusterAttrName,
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2 changes: 1 addition & 1 deletion lib/Dialect/TritonGPU/Transforms/Pipeliner/Schedule.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ void tt::CoarseSchedule::dump() {
// Set <stage, cluster> based on CoarseSchedule.
void tt::CoarseSchedule::serialize(scf::ForOp &forOp) {
for (auto [op, stage, cluster] : getOpsInOrder(forOp)) {
tt::setStageCluster(forOp, op, stage, *cluster);
tt::setStageCluster(op, stage, *cluster);
}
}

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175 changes: 175 additions & 0 deletions test/TritonGPU/samples/descriptor-matmul-pipeline.mlir

Large diffs are not rendered by default.

57 changes: 57 additions & 0 deletions test/TritonGPU/samples/descriptor-matmul-pipeline.mlir.in
Original file line number Diff line number Diff line change
@@ -0,0 +1,57 @@
// To regenerate this test case, run the command
// triton-opt test/TritonGPU/samples/descriptor-matmul-pipeline.mlir.in -tritongpu-loop-scheduling -tritongpu-pipeline -canonicalize | \
// utils/generate-test-checks.py --source test/TritonGPU/samples/descriptor-matmul-pipeline.mlir.in --source_delim_regex="module" \
// -o test/TritonGPU/samples/descriptor-matmul-pipeline.mlir
// RUN: triton-opt %s -split-input-file -tritongpu-loop-scheduling -tritongpu-pipeline -canonicalize | FileCheck --dump-input-context=50 %s
module attributes {"ttg.num-ctas" = 1 : i32, "ttg.num-warps" = 8 : i32, ttg.target = "cuda:90", "ttg.threads-per-warp" = 32 : i32} {
tt.func public @matmul_kernel_with_descriptors(%arg0: !tt.ptr<f16> {tt.divisibility = 16 : i32}, %arg1: !tt.ptr<f16> {tt.divisibility = 16 : i32}, %arg2: !tt.ptr<f16> {tt.divisibility = 16 : i32}, %arg3: i32 {tt.divisibility = 16 : i32}, %arg4: i32 {tt.divisibility = 16 : i32}, %arg5: i32 {tt.divisibility = 16 : i32}) attributes {noinline = false} {
%c8_i32 = arith.constant 8 : i32
%c128_i32 = arith.constant 128 : i32
%c256_i32 = arith.constant 256 : i32
%c0_i32 = arith.constant 0 : i32
%c64_i32 = arith.constant 64 : i32
%c1_i64 = arith.constant 1 : i64
%c1_i32 = arith.constant 1 : i32
%c127_i32 = arith.constant 127 : i32
%c255_i32 = arith.constant 255 : i32
%c63_i32 = arith.constant 63 : i32
%cst = arith.constant dense<0.000000e+00> : tensor<128x256xf32, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>>
%0 = tt.get_program_id x : i32
%1 = arith.addi %arg3, %c127_i32 : i32
%2 = arith.divsi %1, %c128_i32 : i32
%3 = arith.addi %arg4, %c255_i32 : i32
%4 = arith.divsi %3, %c256_i32 : i32
%5 = arith.muli %4, %c8_i32 : i32
%6 = arith.divsi %0, %5 : i32
%7 = arith.muli %6, %c8_i32 : i32
%8 = arith.subi %2, %7 : i32
%9 = arith.minsi %8, %c8_i32 : i32
%10 = arith.remsi %0, %9 : i32
%11 = arith.addi %7, %10 : i32
%12 = arith.remsi %0, %5 : i32
%13 = arith.divsi %12, %9 : i32
%14 = arith.extsi %arg5 : i32 to i64
%15 = tt.make_tensor_descriptor %arg0, [%arg3, %arg5], [%14, %c1_i64] : <f16>, <tensor<128x64xf16>>
%16 = tt.make_tensor_descriptor %arg1, [%arg4, %arg5], [%14, %c1_i64] : <f16>, <tensor<256x64xf16>>
%17 = arith.extsi %arg4 : i32 to i64
%18 = tt.make_tensor_descriptor %arg2, [%arg3, %arg4], [%17, %c1_i64] : <f16>, <tensor<128x256xf16>>
%19 = arith.muli %11, %c128_i32 : i32
%20 = arith.muli %13, %c256_i32 : i32
%21 = arith.addi %arg5, %c63_i32 : i32
%22 = arith.divsi %21, %c64_i32 : i32
%23:2 = scf.for %arg6 = %c0_i32 to %22 step %c1_i32 iter_args(%arg7 = %cst, %arg8 = %c0_i32) -> (tensor<128x256xf32, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>>, i32) : i32 {
%26 = tt.experimental_descriptor_load %15[%19, %arg8] : !tt.tensordesc<tensor<128x64xf16>> -> tensor<128x64xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [4, 2], order = [1, 0]}>>
%27 = ttg.local_alloc %26 : (tensor<128x64xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [4, 2], order = [1, 0]}>>) -> !ttg.memdesc<128x64xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [1, 0], hasLeadingOffset = true}>, #ttg.shared_memory>
%28 = tt.experimental_descriptor_load %16[%20, %arg8] : !tt.tensordesc<tensor<256x64xf16>> -> tensor<256x64xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [4, 2], order = [1, 0]}>>
%29 = ttg.local_alloc %28 : (tensor<256x64xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [4, 2], order = [1, 0]}>>) -> !ttg.memdesc<256x64xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [1, 0], hasLeadingOffset = true}>, #ttg.shared_memory>
%30 = ttg.memdesc_trans %29 {order = array<i32: 1, 0>} : !ttg.memdesc<256x64xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [1, 0], hasLeadingOffset = true}>, #ttg.shared_memory> -> !ttg.memdesc<64x256xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [0, 1], hasLeadingOffset = true}>, #ttg.shared_memory>
%31 = ttng.warp_group_dot %27, %30, %arg7 {inputPrecision = 0 : i32} : !ttg.memdesc<128x64xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [1, 0], hasLeadingOffset = true}>, #ttg.shared_memory> * !ttg.memdesc<64x256xf16, #ttg.shared<{vec = 8, perPhase = 1, maxPhase = 8, order = [0, 1], hasLeadingOffset = true}>, #ttg.shared_memory> -> tensor<128x256xf32, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>>
%32 = arith.addi %arg8, %c64_i32 : i32
scf.yield %31, %32 : tensor<128x256xf32, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>>, i32
}
%24 = arith.truncf %23#0 : tensor<128x256xf32, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>> to tensor<128x256xf16, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>>
%25 = ttg.convert_layout %24 : tensor<128x256xf16, #ttg.nvidia_mma<{versionMajor = 3, versionMinor = 0, warpsPerCTA = [8, 1], instrShape = [16, 256, 16]}>> -> tensor<128x256xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 8], order = [1, 0]}>>
tt.experimental_descriptor_store %18[%19, %20], %25 : !tt.tensordesc<tensor<128x256xf16>>, tensor<128x256xf16, #ttg.blocked<{sizePerThread = [1, 1], threadsPerWarp = [1, 32], warpsPerCTA = [1, 8], order = [1, 0]}>>
tt.return
}
}
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