The mps3_an547_tsv initially was based off of mps3_an547_ns i.e. the non

secure image, but the non secure image is broken in both fork as main in QEMU environment, so used mps3_an547 as a base for mps3_an547_tsv. Have mapped Flash as first section of 16K of SRAM, and the RAM for kernel is bottom 767K of SRAM, have mapped the other 1MB of SRAM0 and 2 MB of SRAM1 to SRAM and ISRAM respectively. | FLASH (16K) in SRAM0 | | 240K (Spare) in SRAM0 | | Kernel (767 K) in SRAM0 | | 1K (Spare) | | 1MB SRAM0 as SRAM | | 1MB SRAM1 as ISRAM | | 1MB SRAM1 as DDR | This is temporary arrangement to make progress. We will revist once we have jtag-uart and other FPGA functionality working.
tsisw · Jul 8, 2024 · c95435b · c95435b
1 parent 85328fd
commit c95435b
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diff --git a/boards/arm/mps3/mps3_an547_tsv.dts b/boards/arm/mps3/mps3_an547_tsv.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2021 Linaro Limited
+ * Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,8 +35,8 @@
 		/*
 		zephyr,shell-uart = &uart0;
 		*/
-		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,sram = &dtcm;
+		zephyr,flash = &itcm;
 	};
 	/*
 	leds {
@@ -48,10 +49,40 @@
 			gpios = <&gpio_led0 1>;
 			label = "USERLED1";
 		};
+		led_2: led_2 {
+			gpios = <&gpio_led0 2>;
+			label = "USERLED2";
+		};
+		led_3: led_3 {
+			gpios = <&gpio_led0 3>;
+			label = "USERLED3";
+		};
+		led_4: led_4 {
+			gpios = <&gpio_led0 4>;
+			label = "USERLED4";
+		};
+		led_5: led_5 {
+			gpios = <&gpio_led0 5>;
+			label = "USERLED5";
+		};
+		led_6: led_6 {
+			gpios = <&gpio_led0 6>;
+			label = "USERLED6";
+		};
+		led_7: led_7 {
+			gpios = <&gpio_led0 7>;
+			label = "USERLED7";
+		};
+		led_8: led_8 {
+			gpios = <&gpio_led0 8>;
+			label = "PB1LED";
+		};
+		led_9: led_9 {
+			gpios = <&gpio_led0 9>;
+			label = "PB2LED";
+		};
 	};
-
 	*/
-
 	/*
 	gpio_keys {
 		compatible = "gpio-keys";
@@ -67,6 +98,20 @@
 		};
 	};
 
+	ethosu {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupt-parent = <&nvic>;
+
+		ethosu0: ethosu@48102000 {
+			compatible = "arm,ethos-u";
+			reg = <0x48102000>;
+			interrupts = <56 3>;
+			secure-enable;
+			privilege-enable;
+			status = "okay";
+		};
+	};
 	*/
 
         jtag_uart: uart@95003000 {
@@ -96,25 +141,25 @@
 	/* We utilize the secure addresses, if you subtract 0x10000000
 	 * you'll get the non-secure alias
 	 */
-	itcm: itcm@4000 {
+	itcm: itcm@60000000 {	/* alias @ 0x60000000 */
 		compatible = "zephyr,memory-region";
-		reg = <0x4000 DT_SIZE_K(16)>;
+		reg = <0x60000000 DT_SIZE_K(16)>;
 		zephyr,memory-region = "ITCM";
 	};
 
-	sram: sram@60010000 {
+	sram: sram@60100000 {	/* alias @ 0x60100000 */
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x60010000 DT_SIZE_K(1024)>;
+		reg = <0x60100000 DT_SIZE_K(1024)>;
 		zephyr,memory-region = "SRAM";
 	};
 
-	dtcm: dtcm@20000000 {
+	dtcm: dtcm@60040000 {	/* alias @ 0x60040000 */
 		compatible = "zephyr,memory-region";
-		reg = <0x20000000 DT_SIZE_K(16)>;
+		reg = <0x60040000 DT_SIZE_K(767)>;
 		zephyr,memory-region = "DTCM";
 	};
 
-	isram: sram@60600000 {
+	isram: sram@60600000 {/* alias @ 0x60600000 */
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x60600000 DT_SIZE_M(1)>;
 		zephyr,memory-region = "ISRAM";
@@ -124,39 +169,17 @@
 	ddr4: memory@60700000 {
 		device_type = "memory";
 		compatible = "zephyr,memory-region";
-		reg = <0x60700000 DT_SIZE_M(1)>;
-		/*
-		       0x70000000 DT_SIZE_M(256)
+		reg = <0x60700000 DT_SIZE_M(1)
+		       /*0x70000000 DT_SIZE_M(256)
 		       0x80000000 DT_SIZE_M(256)
 		       0x90000000 DT_SIZE_M(256)
 		       0xa0000000 DT_SIZE_M(256)
 		       0xb0000000 DT_SIZE_M(256)
 		       0xc0000000 DT_SIZE_M(256)
-		       0xd0000000 DT_SIZE_M(256)>;
-		*/
+		       0xd0000000 DT_SIZE_M(256)*/>;
 		zephyr,memory-region = "DDR4";
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/an547/partition/flash_layout.h
-		 */
-
-		code: memory@60000000 {
-			reg = <0x60000000 DT_SIZE_K(16)>;
-		};
-
-		ram: memory@60010000 {
-			reg = <0x60010000 DT_SIZE_K(1024)>;
-		};
-	};
-
 	soc {
 		peripheral@81000000 {
 			#address-cells = <1>;

diff --git a/boards/arm/mps3/mps3_an547_tsv.yaml b/boards/arm/mps3/mps3_an547_tsv.yaml
@@ -8,14 +8,19 @@ identifier: mps3/an547/tsv
 name: Arm MPS3-AN547_TSV
 type: mcu
 arch: arm
-ram: 2048
-flash: 4
+ram: 767
+flash: 16
 simulation: qemu
 toolchain:
   - gnuarmemb
   - zephyr
   - xtools
+supported:
+  - gpio
 testing:
-  default: true
-  only_tags:
-    - trusted-firmware-m
+  ignore_tags:
+    - drivers
+    - bluetooth
+    - net
+    - timer
+vendor: arm
diff --git a/boards/arm/mps3/mps3_an547_tsv_defconfig b/boards/arm/mps3/mps3_an547_tsv_defconfig
@@ -4,10 +4,10 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-CONFIG_ARM_TRUSTZONE_M=y
 CONFIG_RUNTIME_NMI=y
+CONFIG_ARM_TRUSTZONE_M=n
 CONFIG_ARM_MPU=y
-CONFIG_QEMU_ICOUNT_SHIFT=6
+CONFIG_QEMU_ICOUNT_SHIFT=7
 
 # GPIOs
 CONFIG_GPIO=y
@@ -17,6 +17,5 @@ CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 
-# Build a Non-secure firmware image
+# Build a Secure firmware image
 CONFIG_TRUSTED_EXECUTION_SECURE=n
-CONFIG_TRUSTED_EXECUTION_NONSECURE=y