Add LLVMGen files by ga87puy on llvmgen_base_new at 2023-10-29 22:28:02

tum-ei-eda · Oct 29, 2023 · b6143de · b6143de
1 parent 2ed712d
commit b6143de
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Showing 109 changed files with 102,767 additions and 61 deletions.
diff --git a/ArchImpl/CMakeLists.txt b/ArchImpl/CMakeLists.txt
@@ -40,3 +40,5 @@ ADD_SUBDIRECTORY(RISCV)
 ADD_SUBDIRECTORY(RISCV64)
 ADD_SUBDIRECTORY(RV32IMACFD)
 ADD_SUBDIRECTORY(RV64IMACFD)
+ADD_SUBDIRECTORY(RV32IMACFDXCoreV)
+ADD_SUBDIRECTORY(RV32IMAFDXCoreVHwlp)
diff --git a/ArchImpl/RV32IMACFD/CMakeLists.txt b/ArchImpl/RV32IMACFD/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+# Generated on Sun, 29 Oct 2023 22:27:54 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD.h b/ArchImpl/RV32IMACFD/RV32IMACFD.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArch.h b/ArchImpl/RV32IMACFD/RV32IMACFDArch.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the architecture specific implementation for the RV32IMACFD
  * core architecture.
@@ -34,9 +34,8 @@ extern "C" {
 */
 etiss::int32 RV32IMACFDArch::handleException(etiss::int32 cause, ETISS_CPU * cpu)
 {
-    translate_exc_code(cpu, nullptr, nullptr, cause);
+	translate_exc_code(cpu, nullptr, nullptr, cause);
 	cpu->instructionPointer = cpu->nextPc;
-
 	return 0;
 }
 
@@ -347,7 +346,7 @@ etiss::InterruptVector * RV32IMACFDArch::createInterruptVector(ETISS_CPU * cpu)
 	if (cpu == 0)
 		return 0;
 
-	std::vector<etiss::uint32 *> vec;
+  	std::vector<etiss::uint32 *> vec;
 	std::vector<etiss::uint32 *> mask;
 
 	vec.push_back(&((RV32IMACFD*)cpu)->MIE);

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h b/ArchImpl/RV32IMACFD/RV32IMACFDArchSpecificImp.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the architecture specific header for the RV32IMACFD
  * core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h b/ArchImpl/RV32IMACFD/RV32IMACFDFuncs.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the function macros for the RV32IMACFD core architecture.
  */

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h b/ArchImpl/RV32IMACFD/RV32IMACFDGDBCore.h
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the GDBCore adapter for the RV32IMACFD core architecture.
  *

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFDInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Mon, 02 Oct 2023 18:56:15 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the default
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32AInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32A
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32DC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32DInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32D
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FCInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32FC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32FInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32F
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32IC
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32IInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32I
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_RV32MInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the RV32M
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_ZifenceiInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the Zifencei
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_csrInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the tum_csr
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_retInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the tum_ret
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_rvaInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the tum_rva
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp b/ArchImpl/RV32IMACFD/RV32IMACFD_tum_semihostingInstr.cpp
@@ -1,5 +1,5 @@
 /**
- * Generated on Wed, 04 Oct 2023 17:01:33 +0200.
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
  *
  * This file contains the instruction behavior models of the tum_semihosting
  * instruction set for the RV32IMACFD core architecture.

diff --git a/ArchImpl/RV32IMACFDXCoreV/CMakeLists.txt b/ArchImpl/RV32IMACFDXCoreV/CMakeLists.txt
@@ -0,0 +1,44 @@
+# Generated on Sun, 29 Oct 2023 22:27:54 +0100.
+#
+# This file contains the CMake build info for the RV32IMACFDXCoreV core architecture.
+
+PROJECT(RV32IMACFDXCoreV)
+
+SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
+SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
+
+ADD_LIBRARY(${PROJECT_NAME} SHARED
+	RV32IMACFDXCoreVArch.cpp
+	RV32IMACFDXCoreVArchLib.cpp
+	RV32IMACFDXCoreVArchSpecificImp.cpp
+	RV32IMACFDXCoreVInstr.cpp
+	RV32IMACFDXCoreV_RV32IInstr.cpp
+	RV32IMACFDXCoreV_RV32ICInstr.cpp
+	RV32IMACFDXCoreV_RV32MInstr.cpp
+	RV32IMACFDXCoreV_RV32FInstr.cpp
+	RV32IMACFDXCoreV_RV32FCInstr.cpp
+	RV32IMACFDXCoreV_RV32DInstr.cpp
+	RV32IMACFDXCoreV_RV32DCInstr.cpp
+	RV32IMACFDXCoreV_ZifenceiInstr.cpp
+	RV32IMACFDXCoreV_XCoreVSimdInstr.cpp
+	RV32IMACFDXCoreV_XCoreVBitmanipInstr.cpp
+	RV32IMACFDXCoreV_XCoreVAluInstr.cpp
+	RV32IMACFDXCoreV_XCoreVBranchImmediateInstr.cpp
+	RV32IMACFDXCoreV_XCoreVMemInstr.cpp
+	RV32IMACFDXCoreV_XCoreVMacInstr.cpp
+	RV32IMACFDXCoreV_tum_csrInstr.cpp
+	RV32IMACFDXCoreV_tum_retInstr.cpp
+	RV32IMACFDXCoreV_RV32AInstr.cpp
+	RV32IMACFDXCoreV_tum_rvaInstr.cpp
+	RV32IMACFDXCoreV_tum_semihostingInstr.cpp
+)
+
+add_custom_command(
+	TARGET ${PROJECT_NAME} POST_BUILD
+	COMMAND ${CMAKE_COMMAND} -E copy
+		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+)
+INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
+
+ETISSPluginArch(${PROJECT_NAME})
diff --git a/ArchImpl/RV32IMACFDXCoreV/RV32IMACFDXCoreV.h b/ArchImpl/RV32IMACFDXCoreV/RV32IMACFDXCoreV.h
@@ -0,0 +1,71 @@
+/**
+ * Generated on Sun, 29 Oct 2023 22:27:54 +0100.
+ *
+ * This file contains the registers for the RV32IMACFDXCoreV core architecture.
+ */
+
+#ifndef ETISS_RV32IMACFDXCoreVArch_RV32IMACFDXCoreV_H_
+#define ETISS_RV32IMACFDXCoreVArch_RV32IMACFDXCoreV_H_
+#include <stdio.h>
+#include "etiss/jit/CPU.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#pragma pack(push, 1)
+struct RV32IMACFDXCoreV {
+	ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
+	etiss_uint32 ZERO;
+	etiss_uint32 RA;
+	etiss_uint32 SP;
+	etiss_uint32 GP;
+	etiss_uint32 TP;
+	etiss_uint32 T0;
+	etiss_uint32 T1;
+	etiss_uint32 T2;
+	etiss_uint32 S0;
+	etiss_uint32 S1;
+	etiss_uint32 A0;
+	etiss_uint32 A1;
+	etiss_uint32 A2;
+	etiss_uint32 A3;
+	etiss_uint32 A4;
+	etiss_uint32 A5;
+	etiss_uint32 A6;
+	etiss_uint32 A7;
+	etiss_uint32 S2;
+	etiss_uint32 S3;
+	etiss_uint32 S4;
+	etiss_uint32 S5;
+	etiss_uint32 S6;
+	etiss_uint32 S7;
+	etiss_uint32 S8;
+	etiss_uint32 S9;
+	etiss_uint32 S10;
+	etiss_uint32 S11;
+	etiss_uint32 T3;
+	etiss_uint32 T4;
+	etiss_uint32 T5;
+	etiss_uint32 T6;
+	etiss_uint32 *X[32];
+	etiss_uint32 ins_X[32];
+	etiss_uint32 FENCE[8];
+	etiss_uint8 RES[8];
+	etiss_uint8 PRIV;
+	etiss_uint32 DPC;
+	etiss_uint32 FCSR;
+	etiss_uint32 MSTATUS;
+	etiss_uint32 MIE;
+	etiss_uint32 MIP;
+	etiss_uint32 *CSR[4096];
+	etiss_uint32 ins_CSR[4096];
+	etiss_uint64 F[32];
+	etiss_uint32 RES_ADDR;
+};
+
+#pragma pack(pop) // undo changes
+typedef struct RV32IMACFDXCoreV RV32IMACFDXCoreV; // convenient use of X instead of struct X in generated C code
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif