Instruction Pointer Updated for Illegal Instruction Codes

[JoGei]

When encountering an Illegal Instruction, e.g., false opcode or target registers, the instruction pointer is still updated before the codeblock returns an exception.
When handling the exception the current Instruction Pointer is put in the MEPC such that software can identify the illegal instruction. In ETISS, this is not accurate because the instruction pointer was updated in the illegal instruction with its default increment (+2/+4) which leads to the MEPC being set not to the illegal instruction, but its default successor.

Here is an Example:

etiss/ArchImpl/RV32IMACFD/RV32IMACFD_RV32ICInstr.cpp

Lines 541 to 550 in 0d215c8

	// -----------------------------------------------------------------------------
	partInit.code() += "cpu->instructionPointer = " + std::to_string(ic.current_address_ + 2U) + ";\n";
	if (imm == 0U) {
	partInit.code() += "exception = ETISS_RETURNCODE_ILLEGALINSTRUCTION;\n";
	}
	if ((rd % 32U) != 0U) {
	partInit.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32) + "] = " + std::to_string(((etiss_int32)((imm) << (14)) >> (14))) + ";\n";
	}
	partInit.code() += "if (exception) return exception;\n";
	// -----------------------------------------------------------------------------

Possible fixes, I could think of:

• only update instruction pointer on legal instructions
• store the illegal instruction pointer somewhere to consume by exception handling

[wysiwyng]

this should be fixed in #127, please test.

[JoGei]

Yes looks good. Will close when #127 is upstream.