Update RV32 and RV64 architectures #127
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- semihosting implemented as a jitlib, to be called from the CoreDSL code
…/etiss into maltevonehren-coredsl_exceptions
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Converted to draft until interrupt support is ready |
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New updates:
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| cp.code() = std::string("//EBREAK\n"); | ||
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| // ----------------------------------------------------------------------------- | ||
| { // block |
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For Docu purposes:
Since ebreak now no longer returns etiss::RETURNCODE::CPUFINISHED, what is the proper way to leave the simulation loop besides activating "loop-to-self" flag?
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Simulation exit is possible by loop-to-self with enabled detection or by semihosting, see https://github.com/tum-ei-eda/etiss_riscv_examples/
| *((RV64IMACFD*)parent_.structure_)->X[gprid_] = (etiss_uint64) val; | ||
| } | ||
| }; | ||
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Missing Fields for:
- CSRs
- FPU Registers
- (Vector Registers)
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Will be added later once these can be generated properly by M2-ISA-R
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I have added the needed Fields manually (JoGei@12db114) to test VirtualStruct with this architecture update.
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Tested the interrupt handling for edge-triggered peripheral interrupts in the etiss-sc project with your PR branch. |
This adds updates to the RV32 and RV64 architecture models, namely:
CodePartsfeature, allowing plugins to better insert their own JIT-CodeInterrupt support of these architecture models is currently untested and probably not implemented correctly. Adding interrupt support would be a matter of extending the trap entry function in CoreDSL to handle incoming interrupts, as well as extending ETISS to generate a corresponding call to said trap entry function.
RV64M needs 128 bit arithmetic, this is not supported per se in ETISS, see also #107. This patch uses the GCC
__[u]int128_ttypes for limited support until a better solution is found. Because of this, RV64M only works when using GCC or LLVM as JIT engine, as TCC has no 128-bit arithmetic support.