Update RV32 and RV64 architectures

ArchImpl/CMakeLists.txt

@@ -39,3 +39,4 @@ ADD_SUBDIRECTORY(OR1K)
 ADD_SUBDIRECTORY(RISCV)
 ADD_SUBDIRECTORY(RISCV64)
 ADD_SUBDIRECTORY(RV32IMACFD)
+ADD_SUBDIRECTORY(RV64IMACFD)

ArchImpl/OR1K/OR1KArch.cpp

@@ -358,6 +358,32 @@ void OR1KArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
     {
         etiss_log(ERROR, "Failed to add instructions of the OR1K instruction set");
     }
+
+    mis.foreach(
+        [](etiss::instr::VariableInstructionSet &vis) {
+            vis.foreach(
+                [](etiss::instr::InstructionSet &is) {
+                    is.getInvalid().addCallback(
+                        [](etiss::instr::BitArray &ba, CodeSet &cs, etiss::instr::InstructionContext &ic) {
+                            etiss_uint32 error_code = 0;
+                            static etiss::instr::BitArrayRange R_error_code_0(31, 0);
+                            error_code += R_error_code_0.read(ba) << 0;
+
+                            std::stringstream ss;
+                            ss << "\t\t//trap_entry 32\n";
+                            ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                            //#if DEBUG
+                            ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                            //#endif
+                            ss << "\n";
+                            cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                            return true;
+                        },
+                        0);
+                }
+            );
+        }
+    );
 }
 
 void OR1KArch::initCodeBlock(etiss::CodeBlock &cb) const

ArchImpl/RISCV/RISCVArchSpecificImp.h

@@ -394,6 +394,29 @@ void RISCVArch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
     etiss::instr::VariableInstructionSet *vis = mis.get(1);
     using namespace etiss;
     using namespace etiss::instr;
+
+    vis->foreach(
+        [](InstructionSet &is) {
+            is.getInvalid().addCallback(
+                [](BitArray &ba, CodeSet &cs, InstructionContext &ic) {
+                    etiss_uint32 error_code = 0;
+                    static BitArrayRange R_error_code_0(31, 0);
+                    error_code += R_error_code_0.read(ba) << 0;
+
+                    std::stringstream ss;
+                    ss << "\t\t//trap_entry 32\n";
+                    ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                    //#if DEBUG
+                    ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                    //#endif
+                    ss << "\n";
+                    cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                    return true;
+                },
+                0);
+        }
+    );
+
     vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
         std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRiscvInstrLength =
             [](InstructionContext &ic, etiss_uint32 opRd) {

ArchImpl/RISCV64/RISCV64ArchSpecificImp.h

@@ -418,6 +418,29 @@ void RISCV64Arch::initInstrSet(etiss::instr::ModedInstructionSet &mis) const
 
     using namespace etiss;
     using namespace etiss::instr;
+
+    vis->foreach(
+        [](InstructionSet &is) {
+            is.getInvalid().addCallback(
+                [](BitArray &ba, CodeSet &cs, InstructionContext &ic) {
+                    etiss_uint32 error_code = 0;
+                    static BitArrayRange R_error_code_0(31, 0);
+                    error_code += R_error_code_0.read(ba) << 0;
+
+                    std::stringstream ss;
+                    ss << "\t\t//trap_entry 32\n";
+                    ss << "\t\treturn " << std::to_string(error_code) << "U;";
+                    //#if DEBUG
+                    ss << " // @0x" << std::hex << ic.current_address_ << std::dec << ": " << ba;
+                    //#endif
+                    ss << "\n";
+                    cs.append(CodePart::APPENDEDRETURNINGREQUIRED).code() = ss.str();
+                    return true;
+                },
+                0);
+        }
+    );
+
     vis->length_updater_ = [](VariableInstructionSet &, InstructionContext &ic, BitArray &ba) {
         std::function<void(InstructionContext & ic, etiss_uint32 opRd)> updateRiscvInstrLength =
             [](InstructionContext &ic, etiss_uint32 opRd) {

ArchImpl/RV32IMACFD/CMakeLists.txt

@@ -1,19 +1,21 @@
-# Generated on Wed, 25 May 2022 18:09:21 +0200.
+# Generated on Fri, 03 Nov 2023 13:22:23 +0100.
 #
 # This file contains the CMake build info for the RV32IMACFD core architecture.
 
 PROJECT(RV32IMACFD)
 
+SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
+SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
+
 ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFDArch.cpp
 	RV32IMACFDArchLib.cpp
 	RV32IMACFDArchSpecificImp.cpp
+	RV32IMACFDFuncs.c
 	RV32IMACFDInstr.cpp
-	RV32IMACFD_RISCVBaseInstr.cpp
 	RV32IMACFD_RV32IInstr.cpp
 	RV32IMACFD_RV32ICInstr.cpp
 	RV32IMACFD_RV32MInstr.cpp
-	RV32IMACFD_ZicsrInstr.cpp
 	RV32IMACFD_RV32FInstr.cpp
 	RV32IMACFD_RV32FCInstr.cpp
 	RV32IMACFD_RV32DInstr.cpp
@@ -23,9 +25,15 @@ ADD_LIBRARY(${PROJECT_NAME} SHARED
 	RV32IMACFD_tum_retInstr.cpp
 	RV32IMACFD_RV32AInstr.cpp
 	RV32IMACFD_tum_rvaInstr.cpp
+	RV32IMACFD_tum_semihostingInstr.cpp
 )
 
-FILE(COPY "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}")
+add_custom_command(
+	TARGET ${PROJECT_NAME} POST_BUILD
+	COMMAND ${CMAKE_COMMAND} -E copy
+		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+)
 INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
 
 ETISSPluginArch(${PROJECT_NAME})

ArchImpl/RV32IMACFD/RV32IMACFD.h

@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 01 Mar 2022 00:20:25 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the registers for the RV32IMACFD core architecture.
  */
@@ -54,6 +54,9 @@ struct RV32IMACFD {
 	etiss_uint8 PRIV;
 	etiss_uint32 DPC;
 	etiss_uint32 FCSR;
+	etiss_uint32 MSTATUS;
+	etiss_uint32 MIE;
+	etiss_uint32 MIP;
 	etiss_uint32 *CSR[4096];
 	etiss_uint32 ins_CSR[4096];
 	etiss_uint64 F[32];

ArchImpl/RV32IMACFD/RV32IMACFDArch.cpp

@@ -1,5 +1,5 @@
 /**
- * Generated on Tue, 01 Mar 2022 00:20:25 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -35,8 +35,6 @@
  *********************************************************************************************************************************/
 
 #include "RV32IMACFDArch.h"
-
-#define ETISS_ARCH_STATIC_FN_ONLY
 #include "RV32IMACFDFuncs.h"
 
 #define RV32IMACFD_DEBUG_CALL 0
@@ -67,6 +65,7 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 
 	if (startpointer) cpu->instructionPointer = *startpointer & ~((etiss::uint64)0x1);
 	else cpu->instructionPointer = 0x0;   //  reference to manual
+	cpu->nextPc = cpu->instructionPointer;
 	cpu->mode = 1;
 	cpu->cpuTime_ps = 0;
 	cpu->cpuCycleTime_ps = 31250;
@@ -122,6 +121,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
 	rv32imacfdcpu->PRIV = 0;
 	rv32imacfdcpu->DPC = 0;
 	rv32imacfdcpu->FCSR = 0;
+	rv32imacfdcpu->MSTATUS = 0;
+	rv32imacfdcpu->MIE = 0;
+	rv32imacfdcpu->MIP = 0;
 	for (int i = 0; i < 32; ++i) {
 		rv32imacfdcpu->F[i] = 0;
 	}
@@ -160,6 +162,9 @@ void RV32IMACFDArch::resetCPU(ETISS_CPU * cpu,etiss::uint64 * startpointer)
  	rv32imacfdcpu->X[30] = &rv32imacfdcpu->T5;
  	rv32imacfdcpu->X[31] = &rv32imacfdcpu->T6;
  	rv32imacfdcpu->CSR[3] = &rv32imacfdcpu->FCSR;
+ 	rv32imacfdcpu->CSR[768] = &rv32imacfdcpu->MSTATUS;
+ 	rv32imacfdcpu->CSR[772] = &rv32imacfdcpu->MIE;
+ 	rv32imacfdcpu->CSR[836] = &rv32imacfdcpu->MIP;
 
  	rv32imacfdcpu->PRIV = 3;
  	rv32imacfdcpu->DPC = 0;
@@ -207,7 +212,9 @@ void RV32IMACFDArch::initCodeBlock(etiss::CodeBlock & cb) const
 {
 	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFD.h\"\n");
 	cb.fileglobalCode().insert("#include \"Arch/RV32IMACFD/RV32IMACFDFuncs.h\"\n");
-	cb.functionglobalCode().insert("etiss_uint32 exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->exception = 0;\n");
+	cb.functionglobalCode().insert("cpu->return_pending = 0;\n");
+	cb.functionglobalCode().insert("etiss_uint32 mem_ret_code = 0;\n");
 }
 
 etiss::plugin::gdb::GDBCore & RV32IMACFDArch::getGDBCore()

ArchImpl/RV32IMACFD/RV32IMACFDArch.h

@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the architecture class for the RV32IMACFD core architecture.
  */
@@ -10,6 +10,7 @@
 #include "etiss/CPUArch.h"
 #include "etiss/Instruction.h"
 #include "etiss/InterruptVector.h"
+#include "etiss/InterruptEnable.h"
 #include "RV32IMACFD.h"
 #include "RV32IMACFDGDBCore.h"
 
@@ -89,6 +90,8 @@ class RV32IMACFDArch : public etiss::CPUArch {
 	*/
 	virtual etiss::InterruptVector * createInterruptVector(ETISS_CPU * cpu);
 	virtual void deleteInterruptVector(etiss::InterruptVector * vec, ETISS_CPU * cpu);
+	virtual etiss::InterruptEnable* createInterruptEnable(ETISS_CPU *cpu);
+	virtual void deleteInterruptEnable(etiss::InterruptEnable* en, ETISS_CPU* cpu);
 
 	/**
 		@brief get the GDBcore for RV32IMACFD architecture

ArchImpl/RV32IMACFD/RV32IMACFDArchLib.cpp

@@ -1,5 +1,5 @@
 /**
- * Generated on Thu, 24 Feb 2022 17:15:20 +0100.
+ * Generated on Fri, 03 Nov 2023 13:22:23 +0100.
  *
  * This file contains the library interface for the RV32IMACFD core architecture.
  */