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Removed unnecessary intrinsics structure level
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Having a class that purely wraps a list was a hack around broken syntax
somewhere. Simple to re-add a (better named) class in the event that it
becomes more than a list.
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thomasgoodfellow committed Jan 2, 2025
1 parent 656919f commit c8f81bc
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Showing 12 changed files with 9 additions and 22 deletions.
1 change: 0 additions & 1 deletion examples/cfg/example/intrinsics.yml
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
---
intrinsics:
intrinsics:
- args:
- arg_name: rd
arg_type: i32
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1 change: 0 additions & 1 deletion examples/cfg/example/intrinsics64.yml
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
---
intrinsics:
intrinsics:
- args:
- arg_name: rd
arg_type: i64
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1 change: 0 additions & 1 deletion examples/cfg/openasip/intrinsics.yml
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
---
intrinsics:
intrinsics:
- args:
- arg_name: rs1
arg_type: i32
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1 change: 0 additions & 1 deletion examples/cfg/tumeda/intrinsics.yml
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
---
intrinsics:
intrinsics:
- args:
- arg_name: rd
arg_type: i32
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1 change: 0 additions & 1 deletion examples/cfg/xcorev/XCoreVAlu.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ extensions:
vendor: true
intrinsics:
# See: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-multiply-accumulate-builtins-xcvmac
intrinsics:
# unary
- &ScalarCoreVAluGprIntrinsic
args:
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1 change: 0 additions & 1 deletion examples/cfg/xcorev/XCoreVBitmanip.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ extensions:
vendor: true
intrinsics:
# See: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-bit-manipulation-builtins-xcvbitmanip
intrinsics:
# unary (reg)
- &ScalarCoreVBitmanipGprIntrinsic
args:
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1 change: 0 additions & 1 deletion examples/cfg/xcorev/XCoreVMac.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ extensions:
vendor: true
intrinsics:
# See: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-multiply-accumulate-builtins-xcvmac
intrinsics:
- &ScalarCoreVMacGprGprGprIntrinsic
args:
- arg_name: rd
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1 change: 0 additions & 1 deletion examples/cfg/xcorev/XCoreVSimd.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@ extensions:
vendor: true
intrinsics:
# See: https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md#listing-of-pulp-816-bit-simd-builtins-xcvsimd
intrinsics:
# TODO: add SCI variants
# TODO: add DIV2/4/8 variants
# unary (reg)
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2 changes: 1 addition & 1 deletion seal5/backends/report/test_results/writer.py
Original file line number Diff line number Diff line change
Expand Up @@ -242,7 +242,7 @@ def get_instr_cov(instr_def, tests, settings):
def lookup_intrin(instr_name, settings):
if settings.intrinsics is None:
return None
intrinsics = settings.intrinsics.intrinsics
intrinsics = settings.intrinsics
if not intrinsics:
return None
found = None
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4 changes: 2 additions & 2 deletions seal5/backends/riscv_instr_info/writer.py
Original file line number Diff line number Diff line change
Expand Up @@ -346,9 +346,9 @@ def main():
metrics["success_instructions"].append(instr_def.name)
content = gen_riscv_instr_info_str(instr_def, set_def)
if len(content) > 0:
if args.add_intrinsics and settings.intrinsics.intrinsics:
if args.add_intrinsics and settings.intrinsics:
# TODO: intrinsics should be dict keyed by instr name
for intrinsic in settings.intrinsics.intrinsics:
for intrinsic in settings.intrinsics:
if intrinsic.instr_name.casefold() in [
instr_def.mnemonic.casefold(),
instr_def.name.casefold(),
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6 changes: 3 additions & 3 deletions seal5/backends/riscv_intrinsics/writer.py
Original file line number Diff line number Diff line change
Expand Up @@ -303,7 +303,7 @@ def main():
# errs = []
settings = model.get("settings", None)
llvm_version = None
if not settings or not settings.intrinsics.intrinsics:
if not settings or not settings.intrinsics:
logger.warning("No intrinsics configured; didn't need to invoke intrinsics writer.")
quit() # TODO: refactor this
if settings:
Expand All @@ -329,11 +329,11 @@ def main():
artifacts[set_name] = []
metrics["n_sets"] += 1
ext_settings = set_def.settings
if ext_settings is None or len(settings.intrinsics.intrinsics) == 0:
if ext_settings is None or len(settings.intrinsics) == 0:
metrics["n_skipped"] += 1
metrics["skipped_sets"].append(set_name)
continue
for intrinsic in settings.intrinsics.intrinsics:
for intrinsic in settings.intrinsics:
if intrinsic.set_name is not None and intrinsic.set_name != set_name:
continue
try:
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11 changes: 3 additions & 8 deletions seal5/settings.py
Original file line number Diff line number Diff line change
Expand Up @@ -164,7 +164,7 @@
"sparse_checkout": False,
},
},
"intrinsics": {},
"intrinsics": [],
}


Expand Down Expand Up @@ -626,11 +626,6 @@ class IntrinsicDefn(YAMLSettings):
args: Optional[List[IntrinsicArg]] = None


@dataclass
class IntrinsicsSettings(YAMLSettings):
intrinsics: Optional[List[IntrinsicDefn]] = None


@dataclass
class Seal5Settings(YAMLSettings):
"""Seal5 settings."""
Expand All @@ -652,7 +647,7 @@ class Seal5Settings(YAMLSettings):
riscv: Optional[RISCVSettings] = None
tools: Optional[ToolsSettings] = None
metrics: list = field(default_factory=list)
intrinsics: Optional[IntrinsicsSettings] = None
intrinsics: Optional[List[IntrinsicDefn]] = None

def reset(self):
"""Reset Seal5 seetings."""
Expand Down Expand Up @@ -684,7 +679,7 @@ def reset(self):
transform_info=None,
legalization=None,
)
self.intrinsics = IntrinsicsSettings()
self.intrinsics = []

def save(self, dest: Optional[Path] = None):
"""Save Seal5 settings to file."""
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