Style/Comments from review of #35

ucb-bar · Feb 13, 2019 · 1f58ea1 · 1f58ea1
1 parent efd2f09
commit 1f58ea1
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Showing 4 changed files with 12 additions and 9 deletions.
diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala
@@ -755,10 +755,9 @@ object MacroCompiler extends App {
   def run(args: List[String]) {
     val (params, costParams, forcedMemories) = parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args)
     try {
-      val macros = if (params.get(MacrosFormat) == Some("conf")) {
-        Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
-      } else {
-        Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
+      val macros = params.get(MacrosFormat) match {
+        case Some("conf") => Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
+        case _ => Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
       }
 
       if (macros.nonEmpty) {

diff --git a/macros/src/main/scala/MemConf.scala b/macros/src/main/scala/MemConf.scala
@@ -8,13 +8,13 @@ sealed abstract class MemPort(val name: String) { override def toString = name }
 
 case object ReadPort extends MemPort("read")
 case object WritePort extends MemPort("write")
-case object MaskWritePort extends MemPort("mwrite")
+case object MaskedWritePort extends MemPort("mwrite")
 case object ReadWritePort extends MemPort("rw")
-case object MaskReadWritePort extends MemPort("mrw")
+case object MaskedReadWritePort extends MemPort("mrw")
 
 object MemPort {
 
-  val all = Set(ReadPort, WritePort, MaskWritePort, ReadWritePort, MaskReadWritePort)
+  val all = Set(ReadPort, WritePort, MaskedWritePort, ReadWritePort, MaskedReadWritePort)
 
   def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s)
 

diff --git a/macros/src/main/scala/Utils.scala b/macros/src/main/scala/Utils.scala
@@ -107,7 +107,7 @@ object Utils {
           writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
           input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
         ) }
-      case MaskWritePort => {
+      case MaskedWritePort => {
         val portName = s"W${numW}"
         numW += 1
         MacroPort(
@@ -131,7 +131,7 @@ object Utils {
           input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
           output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))
         ) }
-      case MaskReadWritePort => {
+      case MaskedReadWritePort => {
         val portName = s"RW${numRW}"
         numRW += 1
         MacroPort(

diff --git a/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala b/tapeout/src/main/scala/transforms/RemoveUnusedModules.scala
@@ -8,6 +8,8 @@ import firrtl.passes.Pass
 import firrtl.annotations.{SingleTargetAnnotation, Annotation}
 import firrtl.transforms.DontTouchAnnotation
 
+// Removes all the unused modules in a circuit by recursing through every
+// instance (starting at the main module)
 class RemoveUnusedModules extends Transform {
   def inputForm = MidForm
   def outputForm = MidForm
@@ -48,11 +50,13 @@ class RemoveUnusedModules extends Transform {
 
     val renames = state.renames.getOrElse(RenameMap())
 
+    // This is what the annotation filter should look like, but for some reason it doesn't work.
     //state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Seq()) }
 
     val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main)
     val newAnnos = AnnotationSeq(state.annotations.toSeq.filter { _ match {
       // XXX This is wrong, but it works for now
+      // Tracked by https://github.com/ucb-bar/barstools/issues/36
       case x: DontTouchAnnotation => false
       //case x: DontTouchAnnotation => usedModuleNames contains x.target.module
       case _ => true