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Don't run DCE && Profit
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jwright6323 committed Feb 12, 2019
1 parent 6a51505 commit 5e03ceb
Showing 1 changed file with 3 additions and 6 deletions.
9 changes: 3 additions & 6 deletions macros/src/main/scala/MacroCompiler.scala
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ import firrtl.ir._
import firrtl.PrimOps
import firrtl.Utils._
import firrtl.annotations._
import firrtl.transforms.{NoDCEAnnotation}
import firrtl.CompilerUtils.getLoweringTransforms
import mdf.macrolib.{PolarizedPort, PortPolarity}
import scala.collection.mutable.{ArrayBuffer, HashMap}
Expand Down Expand Up @@ -46,11 +47,6 @@ object MacroCompilerAnnotation {
/** CompileAvailable - compile what is possible and do nothing with uncompiled memories. **/
case object CompileAvailable extends CompilerMode

/**
* The default mode for the macro compiler.
* TODO: Maybe set the default to FallbackSynflops (typical for
* vlsi_mem_gen-like scripts) once it's implemented?
*/
val Default = CompileAvailable

// Options as list of (CompilerMode, command-line name, description)
Expand Down Expand Up @@ -764,7 +760,8 @@ object MacroCompiler extends App {
)
))
)
val state = CircuitState(circuit, HighForm, annotations)
// Append a NoDCEAnnotation to avoid dead code elimination removing the non-parent SRAMs
val state = CircuitState(circuit, HighForm, annotations :+ NoDCEAnnotation)

// Run the compiler.
val result = new MacroCompiler().compileAndEmit(state)
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