Bump to latest rocket-chip

ucb-bar · May 14, 2023 · 03fa0db · 03fa0db
1 parent 27f78da
commit 03fa0db
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Showing 22 changed files with 38 additions and 35 deletions.
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
diff --git a/generators/boom b/generators/boom
diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
@@ -72,17 +72,18 @@ object SpikeCosim
     })
     cosim.io.hartid := hartid.U
     for (i <- 0 until trace.numInsns) {
-      cosim.io.trace(i).valid := trace.insns(i).valid
+      val insn = trace.trace.insns(i)
+      cosim.io.trace(i).valid := insn.valid
       val signed = Wire(SInt(64.W))
-      signed := trace.insns(i).iaddr.asSInt
+      signed := insn.iaddr.asSInt
       cosim.io.trace(i).iaddr := signed.asUInt
-      cosim.io.trace(i).insn := trace.insns(i).insn
-      cosim.io.trace(i).exception := trace.insns(i).exception
-      cosim.io.trace(i).interrupt := trace.insns(i).interrupt
-      cosim.io.trace(i).cause := trace.insns(i).cause
-      cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B
-      cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U)
-      cosim.io.trace(i).priv := trace.insns(i).priv
+      cosim.io.trace(i).insn := insn.insn
+      cosim.io.trace(i).exception := insn.exception
+      cosim.io.trace(i).interrupt := insn.interrupt
+      cosim.io.trace(i).cause := insn.cause
+      cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B
+      cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U)
+      cosim.io.trace(i).priv := insn.priv
     }
   }
 }
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -62,6 +62,7 @@ case class SpikeCoreParams() extends CoreParams {
   val useBitManipCrypto = false
   val useCryptoNIST = false
   val useCryptoSM = false
+  val useConditionalZero = false
 
   override def vLen = 128
   override def vMemDataBits = 128

diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
     val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-    tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
-    tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
-    tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
+    tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+    tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+    tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
 
     system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 

diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -49,7 +49,7 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
 object TileClockGater {
   def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
     val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
-    tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() }
+    tlbus.coupleTo("clock-gater") { gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
     gater.clockNode
   }
 }
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -67,7 +67,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
 object TileResetSetter {
   def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = {
     val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts))
-    tlbus.toVariableWidthSlave(Some("tile-reset-setter")) { setter.tlNode := TLBuffer() }
+    tlbus.coupleTo("tile-reset-setter") { setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
     setter.clockNode
   }
 }
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util._
 import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
-import freechips.rocketchip.tilelink.{TLBuffer}
+import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
 import chipyard.{BuildSystem, DigitalTop}
 import chipyard.clocking._
 import chipyard.iobinders.{IOCellKey, JTAGChipIO}
@@ -33,9 +33,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
   val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
   val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-  tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
-  tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
-  tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
+  tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+  tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+  tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
 
   system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 

diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -165,17 +165,17 @@ trait CanHavePeripheryGCD { this: BaseSubsystem =>
     case Some(params) => {
       if (params.useAXI4) {
         val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p))
-        pbus.toSlave(Some(portName)) {
+        pbus.coupleTo(portName) {
           gcd.node :=
           AXI4Buffer () :=
           TLToAXI4 () :=
           // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx
-          TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
+          TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _
         }
         Some(gcd)
       } else {
         val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p))
-        pbus.toVariableWidthSlave(Some(portName)) { gcd.node }
+        pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
         Some(gcd)
       }
     }

diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -62,7 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
 
   p(InitZeroKey) .map { k =>
     val initZero = LazyModule(new InitZero()(p))
-    fbus.fromPort(Some("init-zero"))() := initZero.node
+    fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
 }
 

diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -67,6 +67,7 @@ case class MyCoreParams(
   val useCryptoNIST: Boolean = false
   val useCryptoSM: Boolean = false
   val traceHasWdata: Boolean = false
+  val useConditionalZero = false
 }
 
 // DOC include start: CanAttachTile

diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -203,7 +203,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
         genOut = FixedPoint(8.W, 3.BP),
         coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
         params = params))
-      pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() }
+      pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingFIR)
     }
     case None => None

diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -132,7 +132,7 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
       val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
-      pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() }
+      pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingPassthroughChain)
     }
     case None => None

diff --git a/generators/cva6 b/generators/cva6
diff --git a/generators/fft-generator b/generators/fft-generator
diff --git a/generators/ibex b/generators/ibex
diff --git a/generators/icenet b/generators/icenet
diff --git a/generators/nvdla b/generators/nvdla
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/sims/firesim b/sims/firesim
+2 −1		src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireDDR3Periphery.scala
+2 −1		src/main/scala/devices/microsemi/polarfire_ddr4/MicrosemiPolarFireDDR4Periphery.scala
+2 −1		src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+2 −1		src/main/scala/devices/xilinx/xilinxvcu118mig/XilinxVCU118MIGPeriphery.scala
+6 −0		src/main/scala/common/parameters.scala
+17 −13		src/main/scala/exu/core.scala
+3 −3		scripts/debug_rom/debug_rom.S
+4 −4		scripts/debug_rom/debug_rom_nonzero.S
+3 −3		src/main/scala/amba/axi4/RegisterRouter.scala
+15 −2		src/main/scala/rocket/ALU.scala
+14 −1		src/main/scala/rocket/IDecode.scala
+184 −0		src/main/scala/rocket/Instructions.scala
+9 −3		src/main/scala/rocket/RocketCore.scala
+8 −0		src/main/scala/subsystem/Configs.scala
+12 −11		src/main/scala/tile/BaseTile.scala
+11 −1		src/main/scala/tile/Core.scala
+8 −9		src/main/scala/tile/RocketTile.scala
+4 −4		src/main/scala/tile/TilePRCIDomain.scala
+25 −24		src/main/scala/tilelink/Atomics.scala
+1 −1		src/main/scala/tilelink/Broadcast.scala
+13 −13		src/main/scala/tilelink/Buffer.scala
+2 −153		src/main/scala/tilelink/BusWrapper.scala
+24 −23		src/main/scala/tilelink/CacheCork.scala
+3 −2		src/main/scala/tilelink/Delayer.scala
+107 −92		src/main/scala/tilelink/Edges.scala
+10 −10		src/main/scala/tilelink/ErrorEvaluator.scala
+21 −20		src/main/scala/tilelink/FIFOFixer.scala
+13 −9		src/main/scala/tilelink/Filter.scala
+35 −34		src/main/scala/tilelink/Fragmenter.scala
+52 −51		src/main/scala/tilelink/Fuzzer.scala
+12 −12		src/main/scala/tilelink/Isolation.scala
+1 −1		src/main/scala/tilelink/Jbar.scala
+3 −3		src/main/scala/tilelink/Map.scala
+36 −35		src/main/scala/tilelink/Metadata.scala
+11 −10		src/main/scala/tilelink/Parameters.scala
+25 −24		src/main/scala/tilelink/PatternPusher.scala
+60 −59		src/main/scala/tilelink/RAMModel.scala
+24 −24		src/main/scala/tilelink/RationalCrossing.scala
+7 −6		src/main/scala/tilelink/RegisterRouter.scala
+1 −1		src/main/scala/tilelink/RegisterRouterTest.scala
+16 −15		src/main/scala/tilelink/SourceShrinker.scala
+5 −5		src/main/scala/tilelink/ToAHB.scala
+7 −7		src/main/scala/tilelink/ToAXI4.scala
+10 −0		src/main/scala/util/Blockable.scala
+2 −2		src/main/scala/BlockDevice.scala
+1 −1		src/main/scala/BootAddrReg.scala
+8 −6		src/main/scala/Dromajo.scala
+1 −1		src/main/scala/Scratchpad.scala
+1 −1		src/main/scala/TileResetCtrl.scala
+42 −54		src/main/scala/TraceIO.scala
+10 −27		sim/firesim-lib/src/main/scala/bridges/DromajoBridge.scala
+14 −19		sim/firesim-lib/src/main/scala/bridges/TracerVBridge.scala
+7 −8		sim/src/main/scala/bridges/TracerVModule.scala