fix naming

ucb-bar · Jan 1, 2024 · 0d7639d · 0d7639d
1 parent b3a620a
commit 0d7639d
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Showing 4 changed files with 6 additions and 7 deletions.
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -23,7 +23,7 @@ class AbstractConfig extends Config(
   new chipyard.harness.WithTieOffInterrupts ++                     // tie-off interrupt ports, if present
   new chipyard.harness.WithTieOffL2FBusAXI ++                      // tie-off external AXI4 master, if present
   new chipyard.harness.WithCustomBootPinPlusArg ++                 // drive custom-boot pin with a plusarg, if custom-boot-pin is present
-  new chipyard.harness.WithChipIdPinFromHarness ++                 // drive chip id pin with a plusarg, if chip id pin is present
+  new chipyard.harness.WithDriveChipIdPin ++                       // drive chip id pin from harness binder, if chip id pin is present
   new chipyard.harness.WithSimUARTToUARTTSI ++                     // connect a SimUART to the UART-TSI port
   new chipyard.harness.WithClockFromHarness ++                     // all Clock I/O in ChipTop should be driven by harnessClockInstantiator
   new chipyard.harness.WithResetFromHarness ++                     // reset controlled by harness
@@ -37,7 +37,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithGPIOCells ++
   new chipyard.iobinders.WithSPIFlashIOCells ++
   new chipyard.iobinders.WithExtInterruptIOCells ++
-  new chipyard.iobinders.WithChipIdPin ++
+  new chipyard.iobinders.WithChipIdIOCells ++
   new chipyard.iobinders.WithCustomBootPin ++
   // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
   // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
@@ -63,7 +63,6 @@ class AbstractConfig extends Config(
   new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
   new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
-  new testchipip.soc.WithChipIdPin ++                               // add a chip id pin for setting chip id in multi-chip configs
   new testchipip.boot.WithCustomBootPin ++                          // add a custom-boot-pin to support pin-driven boot address
   new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
   new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface

diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -237,8 +237,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
   }
 })
 
-//TODO: Allow setting from harness with chipId argument, hardcoding is temporary hack
-class WithChipIdPinFromHarness extends HarnessBinder({
+//TODO: Set with chipId argument to harness binder, hardcoding is temporary hack
+class WithDriveChipIdPin extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: ChipIdPort) => {
     port.io := 0.U
   }

diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -353,7 +353,7 @@ class WithSerialTLIOCells extends OverrideIOBinder({
   }
 })
 
-class WithChipIdPin extends OverrideIOBinder({
+class WithChipIdIOCells extends OverrideIOBinder({
   (system: CanHavePeripheryChipIdPin) => system.chip_id_pin.map({ p =>
     val sys = system.asInstanceOf[BaseSubsystem]
     val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, s"chip_id", sys.p(IOCellKey), abstractResetAsAsync = true)

diff --git a/generators/testchipip b/generators/testchipip
+5 −6		src/main/scala/soc/ChipIdPin.scala
+2 −2		src/main/scala/soc/Configs.scala