Merge pull request #1942 from ucb-bar/nexys-fpga

Nexys video fpga bringup config
ucb-bar · Aug 6, 2024 · 0f888a1 · 0f888a1
2 parents 0e297ff + e84dbd2
commit 0f888a1
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Showing 2 changed files with 77 additions and 8 deletions.
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -22,18 +22,19 @@ class WithNoDesignKey extends Config((site, here, up) => {
 })
 
 // DOC include start: WithNexysVideoTweaks and Rocket
-class WithNexysVideoTweaks extends Config(
+class WithNexysVideoTweaks(freqMHz: Double = 50) extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNexysVideoDDRTL ++
   new WithNoDesignKey ++
   new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
-  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithFrontBusFrequency(50.0) ++
-  new chipyard.config.WithSystemBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
-  new chipyard.config.WithControlBusFrequency(50.0) ++
+  new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
+  new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
+  new chipyard.config.WithFrontBusFrequency(freqMHz) ++
+  new chipyard.config.WithSystemBusFrequency(freqMHz) ++
+  new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
+  new chipyard.config.WithControlBusFrequency(freqMHz) ++
+  new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   new chipyard.config.WithNoDebug ++ // no jtag
@@ -72,3 +73,9 @@ class TinyRocketNexysVideoConfig extends Config(
   new chipyard.config.WithBroadcastManager ++ // no l2
   new chipyard.TinyRocketConfig)
   // DOC include end: WithTinyNexysVideoTweaks and Rocket
+
+class BringupNexysVideoConfig extends Config(
+  new WithNexysVideoSerialTLToGPIO ++
+  new WithNexysVideoTweaks(freqMHz = 75) ++
+  new chipyard.ChipBringupHostConfig)
+
diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala
@@ -3,17 +3,27 @@ package chipyard.fpga.nexysvideo
 
 import chisel3._
 
+import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
 import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
 
-import sifive.blocks.devices.uart.{UARTParams}
+import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
+import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
+import sifive.blocks.devices.pinctrl.{BasePin}
+
+//import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
+import sifive.fpgashells.shell._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.clocks._
 
 import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
+import testchipip.serdes._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
@@ -36,3 +46,55 @@ class WithNexysVideoDDRTL extends HarnessBinder({
     ddrClientBundle <> port.io
   }
 })
+
+// Uses PMOD JA/JB
+class WithNexysVideoSerialTLToGPIO extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SerialTLPort, chipId: Int) => {
+    val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
+    harnessIO <> port.io
+
+    harnessIO match {
+      case io: DecoupledPhitIO => {
+        val clkIO = io match {
+          case io: InternalSyncPhitIO => IOPin(io.clock_out)
+          case io: ExternalSyncPhitIO => IOPin(io.clock_in)
+        }
+        val packagePinsWithPackageIOs = Seq(
+          ("AB22", clkIO),
+          ("AB21", IOPin(io.out.valid)),
+          ("AB20", IOPin(io.out.ready)),
+          ("AB18", IOPin(io.in.valid)),
+          ("Y21", IOPin(io.in.ready)),
+          ("AA21", IOPin(io.out.bits.phit, 0)),
+          ("AA20", IOPin(io.out.bits.phit, 1)),
+          ("AA18", IOPin(io.out.bits.phit, 2)),
+          ("V9", IOPin(io.out.bits.phit, 3)),
+          ("V8", IOPin(io.in.bits.phit, 0)),
+          ("V7", IOPin(io.in.bits.phit, 1)),
+          ("W7", IOPin(io.in.bits.phit, 2)),
+          ("W9", IOPin(io.in.bits.phit, 3))
+        )
+        packagePinsWithPackageIOs foreach { case (pin, io) => {
+          nexysTh.xdc.addPackagePin(io, pin)
+          nexysTh.xdc.addIOStandard(io, "LVCMOS33")
+        }}
+
+        // Don't add IOB to the clock, if its an input
+        io match {
+          case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
+            nexysTh.xdc.addIOB(io)
+          }}
+          case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
+            nexysTh.xdc.addIOB(io)
+          }}
+        }
+
+        nexysTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+        nexysTh.sdc.addGroup(pins = Seq(clkIO))
+        nexysTh.xdc.clockDedicatedRouteFalse(clkIO)
+      }
+    }
+  }
+})
+