Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

.github/scripts/remote-run-firesim-scala-tests.sh

@@ -16,4 +16,4 @@ cd $REMOTE_CHIPYARD_DIR
 # Run Firesim Scala Tests
 export FIRESIM_ENV_SOURCED=1;
 export COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
-make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" testOnly ${mapping[$1]}
+make -C $REMOTE_FIRESIM_DIR JAVA_OPTS="$REMOTE_JAVA_OPTS" SBT_OPTS="$REMOTE_SBT_OPTS" TARGET_SBT_PROJECT="{file:$REMOTE_CHIPYARD_DIR}firechip" testOnly ${mapping[$1]}

build.sbt

@@ -7,13 +7,12 @@ lazy val chipyardRoot = Project("chipyardRoot", file("."))
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
-  scalaVersion := "2.12.10",
+  scalaVersion := "2.13.10",
   assembly / test := {},
   assembly / assemblyMergeStrategy := { _ match {
     case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
     case _ => MergeStrategy.first}},
-  scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
-  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full),
+  scalacOptions ++= Seq("-deprecation","-unchecked"),
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := {
     // drop specific maven dependencies in subprojects in favor of Chipyard's version
@@ -60,17 +59,14 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.5.2"
+val chiselVersion = "3.5.5"
 
 lazy val chiselSettings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
   "org.apache.commons" % "commons-lang3" % "3.12.0",
   "org.apache.commons" % "commons-text" % "1.9"),
   addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
 
-val firrtlVersion = "1.5.1"
-
-lazy val firrtlSettings = Seq(libraryDependencies ++= Seq("edu.berkeley.cs" %% "firrtl" % firrtlVersion))
 
 val chiselTestVersion = "2.5.1"
 
@@ -88,7 +84,7 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -98,7 +94,7 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -108,7 +104,7 @@ lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/bu
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -120,15 +116,14 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.1",
-      "org.apache.commons" % "commons-lang3" % "3.12.0",
+      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
   .settings( // Settings for scalafix
     semanticdbEnabled := true,
     semanticdbVersion := scalafixSemanticdb.revision,
-    scalacOptions += "-Ywarn-unused-import"
+    scalacOptions += "-Ywarn-unused"
   )
 lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
@@ -185,7 +180,7 @@ lazy val hwacha = (project in file("generators/hwacha"))
   .settings(commonSettings)
 
 lazy val boom = (project in file("generators/boom"))
-  .dependsOn(testchipip, rocketchip)
+  .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -242,7 +237,7 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
     commonSettings,
     libraryDependencies ++= Seq(
       "org.scalatest" %% "scalatest" % "3.2.+" % "test",
-      "org.typelevel" %% "spire" % "0.16.2",
+      "org.typelevel" %% "spire" % "0.17.0",
       "org.scalanlp" %% "breeze" % "1.1",
       "junit" % "junit" % "4.13" % "test",
       "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -234,7 +234,14 @@ class WithTieOffInterrupts extends OverrideHarnessBinder({
 
 class WithTieOffL2FBusAXI extends OverrideHarnessBinder({
   (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
-    ports.foreach({ p => p := DontCare; p.bits.tieoff() })
+    ports.foreach({ p =>
+      p.bits := DontCare
+      p.bits.aw.valid := false.B
+      p.bits.w.valid := false.B
+      p.bits.b.ready := false.B
+      p.bits.ar.valid := false.B
+      p.bits.r.ready := false.B
+    })
   }
 })
 
@@ -274,7 +281,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
         d.dmiClock := false.B.asClock
         d.dmiReset := true.B
       case a: ClockedAPBBundle =>
-        a.tieoff()
+        a.pready := false.B
+        a.pslverr := false.B
+        a.prdata := 0.U
+        a.pduser := DontCare
         a.clock := false.B.asClock
         a.reset := true.B.asAsyncReset
         a.psel := false.B

generators/chipyard/src/main/scala/IOBinders.scala

@@ -287,7 +287,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
         p.clock := clockBundle.clock
         p.reset := clockBundle.reset
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }
@@ -307,7 +307,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
         p.clock := clockBundle.clock
         p.reset := clockBundle.reset
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }
@@ -326,7 +326,7 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
         m <> p.bits
         p.clock := clockBundle.clock
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }

generators/chipyard/src/main/scala/TestSuites.scala

@@ -74,11 +74,15 @@ class TestSuiteHelper
           addSuites(env.map(rv32uf))
           if (cfg.fLen >= 64)
             addSuites(env.map(rv32ud))
+          if (cfg.minFLen <= 16)
+            addSuites(env.map(rv32uzfh))
         } else {
           addSuite(rv32udBenchmarks)
           addSuites(env.map(rv64uf))
           if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
+          if (cfg.minFLen <= 16)
+            addSuites(env.map(rv64uzfh))
         }
       }
       if (coreParams.useAtomics) {

generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala

@@ -119,7 +119,8 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN
 class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
   val node = DividerOnlyClockGeneratorNode(pllName)
 
-  lazy val module = new LazyRawModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyRawModuleImp(this) {
     require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator")
     val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head
     val (outClocks, ClockGroupEdgeParameters(_, outSinkParams,  _, _)) = node.out.head

generators/chipyard/src/main/scala/clocking/TileResetSetter.scala

@@ -34,7 +34,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
       }
     })
     tlNode.regmap((0 until nTiles).map({ i =>
-      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)),
+      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
     }): _*)
 
     val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -25,7 +25,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = true))
+      core = tp.tileParams.core.copy(trace = true)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
@@ -36,7 +36,7 @@ class WithTraceIO extends Config((site, here, up) => {
 class WithNoTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = false))
+      core = tp.tileParams.core.copy(trace = false)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = false))
     case other => other

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -62,6 +62,11 @@ case class MyCoreParams(
   val decodeWidth: Int = 1 // TODO: Check
   val fetchWidth: Int = 1 // TODO: Check
   val retireWidth: Int = 2
+  val useBitManip: Boolean = false
+  val useBitManipCrypto: Boolean = false
+  val useCryptoNIST: Boolean = false
+  val useCryptoSM: Boolean = false
+  val traceHasWdata: Boolean = false
 }
 
 // DOC include start: CanAttachTile

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -40,7 +40,7 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils {
       // If a custom test suite is set up, use the custom test suite
       annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
 
-    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
+    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
   }
 
 

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -76,7 +76,7 @@ class WithSerialBridge extends OverrideHarnessBinder({
       val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) {
         SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
       }
-      SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
+      SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool)
     }
     Nil
   }
@@ -97,7 +97,7 @@ class WithUARTBridge extends OverrideHarnessBinder({
     val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
     val pbusClock = pbusClockNode.in.head._1.clock
     BoringUtils.bore(pbusClock, Seq(uartSyncClock))
-    ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
+    ports.map { p => UARTBridge(uartSyncClock, p, th.buildtopReset.asBool)(system.p) }; Nil
 })
 
 class WithBlockDeviceBridge extends OverrideHarnessBinder({
@@ -134,7 +134,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
             axiClockBundle,
             th.buildtopReset)
         }
-        SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName))
+        SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
 
         // connect SimAxiMem
         (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>

project/plugins.sbt

@@ -1,3 +1,3 @@
 addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
-addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21")
+addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
 addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3")